• Journal of the Korean Electrochemical Society
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• v.27 no.2
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• pp.73-79
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• 2024

As the use of fossil fuels has gradually increased, so has the emission of greenhouse gases such as carbon dioxide, leading to environmental problems. As a result, lithium-ion batteries (LiB) have emerged as the solution to this issue. To manufacture medium to large-sized lithium-ion batteries (LiB), it requires electrodes with high capacity and fast charging capabilities. Silicon (Si) is considered a next-generation anode with high-capacity properties, so, reduced graphene oxide (rGO) was compounded with Si@resorcinol-formaldehyde resin (RF) composite to prevent the volume expansion of Si. It was confirmed that the composite anode prepared exhibited improved capacity and enhanced stability.

• Korean Journal of Materials Research
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• v.14 no.6
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• pp.413-419
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• 2004

Recently, Silicon On Insulator (SOI) devices emerged to achieve better device characteristics such as higher operation speed, lower power consumption and latch-up immunity. Nevertheless, there are many detrimental defects in SOI wafers such as hydrofluoric-acid (HF)-defects, pinhole, islands, threading dislocations (TD), pyramid stacking faults (PSF), and surface roughness originating from quality of buried oxide film layer. Although the number of defects in SOI wafers has been greatly reduced over the past decade, the turn over of high-speed microprocessors using SOI wafers has been delayed because of unknown defects in SOI wafers. A new characterization method is proposed to investigate the crystalline quality, the buried oxide integrity and some electrical parameters of bonded SOI wafers. In this study, major surface defects in bonded SOI are reviewed using HF dipping, Secco etching, Cu-decoration followed by focused ion beam (FIB) and transmission electron microscope (TEM).

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.12
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• pp.68-74
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• 1998

Improved performance and suppressed short-channel effects of polysilicon thin film transistors (poly-Si TFTs) with very thin electron cyclotron resonance (ECR) $N_2$O-plasma gate oxide have been investigated. Poly-Si TFTs with ECR $N_2$O-plasma oxide ($N_2$O-TFTs) show better performance as well as suppressed short-channel effects than those with conventional thermal oxide. The fabricated $N_2$O-TFTs do not show threshold voltage reduction until the gate length is reduced to 3 ${\mu}{\textrm}{m}$ for n-channel and 1 ${\mu}{\textrm}{m}$ for p-channel, respectively. The improvements are due to the smooth interface, passivation effects, and strong Si ≡ N bonds.

• Corrosion Science and Technology
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• v.14 no.3
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• pp.127-131
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• 2015

Model alloys Fe-9Cr, Fe-20Cr and Fe-20Cr-20Ni (wt. %) with 0.1 and 0.2 % Si were exposed to $Ar-20CO_2-20H_2O$ gas at $818^{\circ}C$. The undoped alloys formed a thick iron-rich oxide scale. The additions of Si reduced scaling rates of Fe-9Cr to some extent but significantly suppressed the formation of iron oxide scales on Fe-20Cr and Fe-20Cr-20Ni. Carburisation also occurred in all undoped alloys, but not in Si-containing Fe-20Cr and Fe-20Cr-20Ni. Protection against carburisation was a result of the formation of an inner scale layer of silica.

• KIEE International Transactions on Electrophysics and Applications
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• v.3C no.1
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• pp.28-32
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• 2003

In this paper, we have studied the in-situ end point detection (EPD) for direct chemical mechanical polishing (CMP) of shallow trench isolation (STI) structures without the reverse moat etch process. In this case, we applied a high selectivity $1n (HSS) that improves the silicon oxide removal rate and maximizes oxide to nitride selectivity Quite reproducible EPD results were obtained, and the wafer-to-wafer thickness variation was significantly reduced compared with the conventional predetermined polishing time method without EPD. Therefore, it is possible to achieve a global planarization without the complicated reverse moat etch process. As a result, the STI-CMP process can be simplified and improved using the new EPD method.

• ETRI Journal
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• v.19 no.4
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• pp.402-413
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• 1997

A CMOS device which has an extended heavily-doped amorphous silicon source/drain layer on the field oxide and an amorphous silicon local interconnection (ASLI) layer in the self-aligned source/drain region has been studied. The ASLI layer has some important roles of the local interconnections from the extended source/drain to the bulk source/drain and the path of the dopant diffusion sources to the bulk. The junction depth and the area of the source/drain can be controlled easily by the ASLI layer thickness. The device in this paper not only has very small area of source/drain junctions, but has very shallow junction depths than those of the conventional CMOS device. An operating speed, however, is enhanced significantly compared with the conventional ones, because the junction capacitance of the source/drain is reduced remarkably due to the very small area of source/drain junctions. For a 71-stage unloaded CMOS ring oscillator, 128 ps/gate has been obtained at power supply voltage of 3.3V. Utilizing this proposed structure, a buried channel PMOS device for the deep submicron regime, known to be difficult to implement, can be fabricated easily.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.449-452
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• 1998

We have studied the oxidatio nrte of $Si_{1-x}Ge_{x}$ epitaxial layer grown by MBE(molecular beam epitaxy). Oxidation were performed at 700.deg. C, 800.deg. C, 900.deg. C, and 1000.deg. C. After the oxidation, the results of AES(auger electron spectroscopy) showed that Ge was completely rejected out of the oxide and pile up at $SiO_{2}/$Si_{1-x}Ge_{x}$ interface. It is shown that the presence of Ge at the $SiO_{2}$/$Si_{1-x}Ge_{x}$ interface changes the dry oxidation rate. The dry oxidation rate was equal to that of pure Si regardless of Ge mole fraction at 700.deg. C and 800.deg.C, while it was decreased at both 900.deg. C and 1000.deg.C as the Ge mole fraction was increased. The ry oxidation rates were reduced for heavy Ge concentration, and large oxidation time. In the parabolic growth region of $Si_{1-x}Ge_{x}$ oxidation, The parabolic rate constant are decreased due to the presence of Ge-rich layer. After the longer oxidation at the 1000.deg.C, AES showed that Ge peak distribution at the $SiO_{2}$/$Si_{1-x}Ge_{x}$ interface reduced by interdiffusion of silicon and germanium.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.1
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• pp.71-74
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• 2006

In this paper, we investigated the characterization of silicon oxide(SiOx) thin film on Ethylene Terephthalate(PET) substrates by e-beam deposition for transparent barrier application. The temperature of chamber increases from $30^{\circ}C$ to $110^{\circ}C$, the roughness increase while the Water vapor transmission rate (WVTR) decreases. Under these conditions, the WVTR for PET can be reduced from a level of $0.57 g/m^2/day$ (bare subtrate) to $0.05 g/m^2/day$ after application of a 200-nm-thick $SiO_2$ coating at 110 C. A more efficient way to improve permeation of PET was carried out by using a double side coating of a 5-${\mu}m$-thick parylene film. It was found that the WVTR can be reduced to a level of $-0.2 g/m^2/day$. The double side parylene coating on PET could contribute to the lower stress of oxide film, which greatly improves the WVTR data. These results indicates that the $SiO_2$ /Parylene/PET barrier coatings have high potential for flexible organic light-emitting diode(OLED) applications.

• Journal of the Korean Vacuum Society
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• v.13 no.3
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• pp.120-126
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• 2004

A damage-reduced trench was investigated in view of the defect distribution along trench sidewall and bottom using high resolution transmission electron microscopy, which was formed by HBr plasma and additive gases in magnetically enhanced reactive ion etching system. Adding $O_2$ and other additive gases into HBr plasma makes it possible to eliminate sidewall undercut and lower surface roughness by forming the passivation layer of lateral etching. To reduce the RIE induced damage and obtain the fine shape trench corner rounding, we investigated the hydrogen annealing effect after trench formation. Silicon atomic migration on trench surfaces using high temperature hydrogen annealing was observed with atomic scale view. Migrated atoms on crystal surfaces formed specific crystal planes such as (111), (113) low index planes, instead of fully rounded comers to reduce the overall surface energy. We could observe the buildup of migrated atoms against the oxide mask, which originated from the surface migration of silicon atoms. Using this hydrogen annealing, more uniform thermal oxide could be grown on trench surfaces, suitable for the improvement of oxide breakdown.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.416-419
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• 1987

The miniaturization of Bird's Beak generated at the field oxidation has been studied by adding polysilicon layer between the silicon nitride and pad oxide stack, which is the basic structure of Conventional LOCOS. The size and shape of Bird's Beak were intensively observed by SEM, and also the electrical characteristics of Bird's Beak-reduced LOCOS structure were compared with those of Conventional LOCOS. The length of Bird's Beak was reached up to $0.20-0.28{\mu}m$, while about to $0.50-0.53{\mu}m$ in conventional LOCOS, resulting in 60% reduction.