• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.10
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• pp.1702-1705
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• 2016

We propose a novel hydrogen-reduced p-type amorphous silicon oxide buffer layer between $TiO_2$ antireflection layer and p-type silicon window layer of silicon thin film solar cells. This new buffer layer can protect underlying the $TiO_2$ by suppressing hydrogen plasma, which could be made by excluding $H_2$ gas introduction during plasma deposition. Amorphous silicon oxide thin film solar cells with employing the new buffer layer exhibited better conversion efficiency (8.10 %) compared with the standard cell (7.88 %) without the buffer layer. This new buffer layer can be processed in the same p-chamber with in-situ mode before depositing main p-type amorphous silicon oxide window layer. Comparing with state-of-the-art buffer layer of AZO/p-nc-SiOx:H, our new buffer layer can be processed with cost-effective, much simple process based on similar device performances.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.2
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• pp.125-130
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• 2000

Two step growth of reduced pressure chemical vapor eposition has been successfully developed to achieve in-situ phosphorus-doped silicon epilayers, and the characteristic evolution on their microstructures has been investigated using scanning electron microscopy, transmission electron microscopy, and secondary ion mass spectroscopy. The two step growth, which employs heavily in-situ P doped silicon buffer layer grown at low temperature, proposes crucial advantages in manipulating crystal structures of in-situ phosphorus doped silicon. In particular, our experimental results showed that with annealing of the heavily P doped silicon buffer layers, high-quality epitaxial silicon layers grew on it. the heavily doped phosphorus in buffer layers introduces into native oxide and plays an important role in promoting the dispersion of native oxides. Furthermore, the phosphorus doping concentration remains uniform depth distribution in high quality single crystalline Si films obtained by the two step growth.

• Korean Journal of Materials Research
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• v.12 no.9
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• pp.724-728
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• 2002

Inductively-coupled $N_2$O plasma was utilized to grow silicon dioxide at low temperature and applied to fabricate polycrystalline-silicon thin film transistors. At $400^{\circ}C$, the thickness of oxide was limited to 5nm and the oxide contained Si≡N and ≡Si-N-Si≡ bonds. The nitrogen incorporation improved breakdown field to 10MV/cm and reduced the interface charge density to $1.52$\times$10^{11}$ $cm^2$ with negative charge. The $N_2$O plasma gate oxide enhanced the field effect mobility of polycrystalline thin film transistor, compared to $O_2$ plasma gate oxide, due to the reduced interface charge at the $Si/SiO_2$ interface and also due to the reduced trap density at Si grain boundaries by nitrogen passivation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.354-357
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• 2002

Thermally grown gate oxide on 4H-SiC wafer was investigated. The oxide layers were grown at l150$^{\circ}C$ varying the carrier gas and post activation annealing conditions. Capacitance-Voltage(C-V) characteristic curves were obtained and compared using various gate electrode such as Al, Ni and poly-Si. The interface trap density can be reduced by using post oxidation annealing process in Ar atmosphere. All of the samples which were not performed a post oxidation annealing process show negative oxide effective charge. The negative oxide effective charges may come from oxygen radical. After the post oxidation annealing, the oxygen radicals fixed and the effective oxide charge become positive. The effective oxide charge is negative even in the annealed sample when we use poly silicon gate. Poly silicon layer was dope by POCl$_3$ process. The oxide layer may be affected by P ions in poly silicon layer due to the high temperature of the POCl$_3$ doping process.

• Journal of Surface Science and Engineering
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• v.31 no.2
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• pp.101-108
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• 1998

The effect of oxidation-reduction heating conditions on coating adherence of hot-dip galvanized steel containing silicon has beeninvestigated. The presence of a stbke sillicon oxide formed on the steel surface has been shown to be very detrimenal to proper wetting by liquid zinc. When the steel has more than the critical sillicon content neeled to from a stable external oxide, the use of oxidation-reduction method has been found successful in obtaining a good quality, coated product with excellence adhreence. This can be explained by the formation of an iron oxide. The iron oxrtion of the scale is reduced, leaving the stable oxides dispersed in a fresh metallic iron surface layer. This reduced iron surface is easily wetted by the liquid zinc and excellent adherence is obtained.

• Transactions on Electrical and Electronic Materials
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• v.16 no.6
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• pp.312-316
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• 2015

Through silicon via (TSV) technology holds the promise of chip-to-chip or chip-to-package interconnections for higher performance with reduced signal delay and power consumption. It includes high aspect ratio silicon etching, insulation liner deposition, and seamless metal filling. The desired etch profile should be straightforward, but high aspect ratio silicon etching is still a challenge. In this paper, we investigate the use of etch hard mask for finer TSVs etching to have clear definition of etched via pattern. Conventionally employed photoresist methods were initially evaluated as reference processes, and oxide and metal hard mask were investigated. We admit that pure metal mask is rarely employed in industry, but the etch result of metal mask support why hard mask are more realistic for finer TSV etching than conventional photoresist and oxide mask.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.12
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• pp.106-114
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• 1994

The local oxidation of silicon (LOCOS) technology, which uses a silicon nitride film as an oxidation mask and a pad oxide beween the silicon nitride and the silicon substrate, has been widely used in integrated circuits for process simplicity. But, due to long brid's beak length, there are difficulties in scabilities. Many advanced isolation techniques have been wuggested for the feduction of bird's beak length. In this paper, we presented reduced bird's beak length using the polybuffered oxide and the silicon nitride as the sidewall. Also, investigating the electrical behavior of the parasitic Al-gate MOSFET on LOCOS, we proved the validity for new isolation process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.5
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• pp.364-369
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• 2011

Analyzing electrical degradation of polycrystalline silicon transistor to applicable at several environment is very important issue. In this research, after fabricating p channel poly crystalline silicon TFT (thin film transistor) electrical characteristics were compare and analized that changed by gate bias with first measurement. As a result on and off current was reduced by variation of gate bias and especially re duce ratio of off current was reduced by $7.1{\times}10^1$. On/off current ratio, threshold voltage and electron mobility increased. Also, when channel length gets shorter on/off current ratio was increased more and thresh old voltage increased less. It was cause due to electron trap and de-trap to gate silicon oxide by variation of gate bias.

• Bulletin of the Korean Chemical Society
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• v.18 no.7
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• pp.737-740
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• 1997

The influence of cyclic treatments with H2O2/DIW (1 : 10) and HF/DIW (1 : 100) on the roughness of silicon surface in the wet chemical processing was investigated by atomic force microscopy (AFM). During the step of the SC-1 cleaning, there is a large increase in roughness on the silicon surface which will result in the poor gate oxide breakdown properties. The roughness of the silicon wafer after the SC-1 cleaning step was reduced by cyclic treatments of hydrogen peroxide solution and hydrofluoric acid solution instead of HF-only cleaning. AFM images after each step clearly illustrated that the average roughness of silicon surface after three times treatments with H2O2 and HF solutions was reduced by 10 times compared with that after the SC-1 cleaning step.

• Journal of the Society of Disaster Information
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• v.18 no.3
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• pp.478-486
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• 2022

Purpose: Although the working environment is measured at the construction site, only a few noise and vibration that are typically exposed for each process are performed without measuring the working environment by segmenting the exposed harmful factors. Therefore, it is intended to find the harmfulness of silicon oxide dust, which is most exposed at construction sites, and the complementary points of improvement measures currently being implemented at construction sites. Method: The status was analyzed using the actual condition survey report issued by the Korea Occupational Health Corporation and the Korea Occupational Health Association and data from the work environment measurement institution, and compared and analyzed with the rules on work environment measurement of the Occupational Safety and Health Act. Result: The harmfulness of silicon oxide dust was identified and improvement measures were derived. Conclusion: It is expected that occupational diseases against silicon dust can be reduced if the harmfulness of silicon oxide dust at construction sites is derived and improvement measures are actively applied at the site.