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http://dx.doi.org/10.4313/JKEM.2011.24.5.364

A Study on Electric Characteristics of Silicon Implanted p Channel Polycrystalline Silicon Thin Film Transistors Fabricated on High Temperature  

Lee, Jin-Min (Institute of Research and Development, ElnT.Co.,Ltd.)
Publication Information
Journal of the Korean Institute of Electrical and Electronic Material Engineers / v.24, no.5, 2011 , pp. 364-369 More about this Journal
Abstract
Analyzing electrical degradation of polycrystalline silicon transistor to applicable at several environment is very important issue. In this research, after fabricating p channel poly crystalline silicon TFT (thin film transistor) electrical characteristics were compare and analized that changed by gate bias with first measurement. As a result on and off current was reduced by variation of gate bias and especially re duce ratio of off current was reduced by $7.1{\times}10^1$. On/off current ratio, threshold voltage and electron mobility increased. Also, when channel length gets shorter on/off current ratio was increased more and thresh old voltage increased less. It was cause due to electron trap and de-trap to gate silicon oxide by variation of gate bias.
Keywords
Polycrystalline silicon thin film transistor; Degradation; Reverse bias; Ubiquitous sensor network; High temperature p channel;
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