• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.3
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• pp.166-176
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• 2007

Radio frequency (RF) microelectromechanical systems (MEMS) have been pursued for more than a decade as a solution of high-performance on-chip fixed, tunable and reconfigurable circuits. This paper reviews our research work on RF MEMS switches and switching circuits in the past five years. The research work first concentrates on the development of lateral DC-contact switches and capacitive shunt switches. Low insertion loss, high isolation and wide frequency band have been achieved for the two types of switches; then the switches have been integrated with transmission lines to achieve different switching circuits, such as single-pole-multi-throw (SPMT) switching circuits, tunable band-pass filter, tunable band-stop filter and reconfigurable filter circuits. Substrate transfer process and surface planarization process are used to fabricate the above mentioned devices and circuits. The advantages of these two fabrication processes provide great flexibility in developing different types of RF MEMS switches and circuits. The ultimate target is to produce more powerful and sophisticated wireless appliances operating in handsets, base stations, and satellites with low power consumption and cost.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.2944-2946
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• 1999

In this paper, digital circuit evolution is proposed as an intrinsic evolvable system. Evolutionary hardware is a reconfigurable one which adapt itself to the environment and evolve its structure to realize desired performance. By using special FPGA and genetic algorithm, we have made a prototype of intrinsic hardware evolution system. As an example for digital circuit evolution, full adder realization is performed. As the result of this, a very complex structure of digital circuit performing full adder was created. Analysis made on the hardware revealed that some undetermined circuits were developed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.199-203
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• 2017

Mutually-actuated-nano-electromechanical (MA-NEM) memory switches are proposed for scalability improvement. While conventional NEM memory switches have fixed electrode lines, the proposed MA-NEM memory switches have mutually-actuated cantilever-like electrode lines. Thus, MA-NEM memory switches show smaller deformations of beams in switching. This unique feature of MA-NEM memory switches allows aggressive reduction of the beam length while maintaining nonvolatile property. Also, the scalability of MA-NEM memory switches is confirmed by using finite-element (FE) simulations. MA-NEM memory switches can be promising solutions for reconfigurable logic (RL) circuits.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.1187-1188
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• 2008

An area of research called evolvable hardware has recently emerged which combines aspects of evolutionary computation with hardware design and synthesis. Evolvable hardware (EHW) is hardware that can change its own circuit structure by genetic learning to achieve maximum adaptation to the environment. In conventional EHW, the learning is executed by software on a computer. In this paper, we have studied and surveyed a gate-level evolvable hardware chip, by integrating both GA hardware and reconfigurable hardware within a single LSI chip. The chip consists of genetic algorithm(GA) hardware, reconfigurable hardware logic, and the control logic. In this paper, we describe the architecture, functions of the chip.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.415-422
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• 2013

In this paper, we present Self-Checking look-up-table (LUT) based on Scalable Error Detection Coding (SEDC) scheme for use in fault-tolerant reconfigurable architectures. SEDC scheme has shorter latency than any other existing coding schemes for all unidirectional error detection and the LUT execution time remains unaffected with self-checking capabilities. SEDC scheme partitions the contents of LUT into combinations of 1-, 2-, 3- and 4-bit segments and generates corresponding check codes in parallel. We show that the proposed LUT with SEDC performs better than LUT with traditional Berger as well as Partitioned Berger Coding schemes. For 32-bit data, LUT with SEDC takes 39% less area and 6.6 times faster for self-checking than LUT with traditional Berger Coding scheme.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.64-71
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• 2014

Multiplier performs a complex arithmetic operation in various signal processing algorithms such as multimedia and communication system. The multiplier also suffers from its relatively large signal propagation delay, high power dissipation, and large area requirement. This paper presents memristor-CMOS based reconfigurable multiplier reducing area occupation of the multiplier circuitry and increasing compatibility using optimized bit-width for various applications. The performance of the memristor-CMOS based reconfigurable multiplier are estimated with memristor SPICE model and 180 nm CMOS process under 1.8 V supply voltage. The circuit shows performance improvement of 61% for area, 38% for delay and 28% for power consumption respectively compared with the conventional reconfigurable multipliers. It also has an advantage for area reduction of 22% against a twin-precision multiplier.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.1
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• pp.80-83
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• 2017

In this paper, the X-band reconfigurable frequency selective surface having flexible geometry was proposed. The proposed RFSS is composed of patterns of cross-shaped loop with inductive stub, which can control the frequency response for C-Band and X-band by ON/OFF state of PIN diode. To minimize the parasitic effect and to obtain the high level of isolation between the unit cell of FSS and the bias circuit, we designed the grid type bias line on bottom layer through via hole. The measured transmission characteristics show good agreement with the simulation results and good stability of frequency response for different incident angles and curvatures of surface.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.12
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• pp.1112-1115
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• 2015

Recently, there have been advancements in radar related material technology, circuit design techniques and architecture design techniques. These have led to developments in radars' performance while decreasing the costs. Many studies have been carried out to apply radars to multipurpose application. In this study, a reconfigurable S-/X- band radar structure for multipurpose application is proposed and implemented. This radar measures a $51.2cm{\times}50.6cm$ target for 10 times from 2 m to 6 m range with 0.25 m distance step. The measured results show that this radar has 26.40 cm maximum range error, 5.63 cm average range error, and 0.24 cm range error variance at S-band while it has 8.53 cm maximum range error, 2.52 cm average range error, and 0.04 cm range error variance at X-band.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.1
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• pp.46-52
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• 2010

A compact circular microstrip patch antenna with a switchable circular polarization(CP) is proposed at 2.4 GHz. An unequal cross-shaped slot on a ground plane is utilized as a perturbation. By switching pin diodes mounted on the slot, the CP sense of each antenna can be simply switched from left-handed(LH) CP to right-handed(RH) CP vice versa. Since the perturbation can be made on the ground plane and no bias circuit is required on the patch side, the bias circuit has not effect on the main beam radiation. From the experimental results, the impedance bandwidth and CP bandwidth of the proposed antenna have shown up to 150 MHz and 35 MHz, respectively. The peak gain of the proposed antenna is 1.7 dBi for both CP senses.

• Journal of Advanced Navigation Technology
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• v.16 no.6
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• pp.1038-1043
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• 2012

In this work, a high tunable capacitor using a multi-layer dielectric of BZN/BST/BZN is designed and characterized for reconfigurable RF applications. By utilizing a high tunable BST ferroelectric and a low-loss BZN paraelectric thin film, a multi-layer dielectric of BZN/BST/BZN obtained a tunability of 47 % and $tan{\delta}$ of 0.005. The fabricated tunable capacitor on a quartz wafer using this multi-layer dielectric achieved a Q-factor of 10 and tunability of 60 % at 800 MHz and 15 V. Its size is $327{\times}642{\mu}m2$.