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http://dx.doi.org/10.5573/JSTS.2013.13.5.415

Self-Checking Look-up Tables using Scalable Error Detection Coding (SEDC) Scheme  

Lee, Jeong-A (School of Electronics Engineering, Kyungpook National University)
Siddiqui, Zahid Ali (School of Electronics Engineering, Kyungpook National University)
Somasundaram, Natarajan (School of Electronics Engineering, Kyungpook National University)
Lee, Jeong-Gun (School of Electronics Engineering, Kyungpook National University)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.13, no.5, 2013 , pp. 415-422 More about this Journal
Abstract
In this paper, we present Self-Checking look-up-table (LUT) based on Scalable Error Detection Coding (SEDC) scheme for use in fault-tolerant reconfigurable architectures. SEDC scheme has shorter latency than any other existing coding schemes for all unidirectional error detection and the LUT execution time remains unaffected with self-checking capabilities. SEDC scheme partitions the contents of LUT into combinations of 1-, 2-, 3- and 4-bit segments and generates corresponding check codes in parallel. We show that the proposed LUT with SEDC performs better than LUT with traditional Berger as well as Partitioned Berger Coding schemes. For 32-bit data, LUT with SEDC takes 39% less area and 6.6 times faster for self-checking than LUT with traditional Berger Coding scheme.
Keywords
Self-checking circuit; error detection coding; unidirectional transient errors; look-up table; reconfigurable architecture;
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1 J. R. Schwank et al., "Radiation effects in MOS Oxides," IEEE Trans. Nucl. Sci. vol. 55, no. 4, pp. 1833-1853, 2008.   DOI   ScienceOn
2 B. Bose, and D. K. Pradhan, "Optimal Unidirectional Error Detecting/Correcting Codes," IEEE Trans. Comput. vol. C-31, no. 6, pp. 564-568, 1982.   DOI   ScienceOn
3 E. Stott, P. Sedcole, and P. Cheung, "Fault Tolerant methods for reliability in FPGAs," Proc. Int. Conf. Field Programmable Logic, pp. 415-420, 2008.
4 R. V. Kshirsagar, and R. M. Patrikar, "A novel fault tolerant design and an algorithm for tolerating faults in digital circuits," Proc. 3rd Int. Design and Test Workshop (IDT) pp. 148-153, 2008.
5 N. Alves, "State-of-the-Art techniques for detecting transient errors in electrical circuits," IEEE Potentials vol. 30, no. 3, pp. 30-35, 2011.
6 A. Morozov et al., "New self-checking circuits by use of Berger-codes," Proc. IEEE Int. On-Line Testing pp. 141-146, 2000.
7 D.A. Pierce Jr, and P.K. Lala, "Modular Implementation of Efficient Self-Checking Checkers for the Berger Code," J. of Electronic Testing: Theory and Applicat., vol. 9, no. 3, pp. 279-294, 1996.   DOI
8 S. Natarajan, J. A. Lee, and J. G. Lee, Scalable Error Detection Coding (SEDC) Generator, Self- Checking look-up Table having the Generator and Method of Scalable Error detection Coding, Korean Patent Application no. 10-2011-0098730, filed 29 September 2011.
9 N. K. Jha, and S. J. Wang, "Design and Synthesis of Self-Checking VLSI Circuits", in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 6, pp. 878-887, 1993.   DOI   ScienceOn
10 D. K. Pradhan, and J. J. Stiffler, "Error-Correcting Codes and Self-Checking Circuits", in Computer, vol. 13, no. 3, pp. 27-37, 1980.
11 D. A. Anderson, and G. Metze, "Design of Totally Self-Checking Check Circuits for m-Out-of-n Codes", in IEEE Transactions on Computers, vol. C-22, no. 3, pp. 263-269, 1973.   DOI   ScienceOn
12 G. M. Koob, and C. G. Lau, Foundations of Dependable computing: System Implementation, Kluwer Academic Publishers, 1994.
13 J. E. Smith, and G. Metze, "Stronlgy Fault Secure Logic Networks", in IEEE Transactions on Computers, vol. C-27, no. 6, pp. 491-499, 1978.   DOI   ScienceOn
14 C. Metra, M. Favalli, and B. Ricco, "Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines", in IEEE Transactions on Computers, vol. 49, no. 6, pp. 560- 574, 2000.   DOI   ScienceOn