• Korean Journal of Metals and Materials
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• v.49 no.5
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• pp.388-394
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• 2011

High speed copper filling into TSV (through-silicon-via) for three dimensional stacking of Si chips was investigated. For this study, a tapered via was prepared on a Si wafer by the DRIE (deep reactive ion etching) process. The via had a diameter of 37${\mu}m$ at the via opening, and 32${\mu}m$ at the via bottom, respectively and a depth of 70${\mu}m$. $SiO_2$, Ti, and Au layers were coated as functional layers on the via wall. In order to increase the filling ratio of Cu into the via, a PPR (periodic pulse reverse) wave current was applied to the Si chip during electroplating, and a PR (pulse reverse) wave current was applied for comparison. After Cu filling, the cross sections of the vias was observed by FE-SEM (field emission scanning electron microscopy). The experimental results show that the tapered via was filled to 100% at -5.85 mA/$cm^2$ for 60 min of plating by PPR wave current. The filling ratio into the tapered via by the PPR current was 2.5 times higher than that of a straight via by PR current. The tapered via by the PPR electroplating process was confirmed to be effective to fill the TSV in a short time.

• Transactions on Electrical and Electronic Materials
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• v.15 no.2
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• pp.91-95
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• 2014

This paper presents the structure and process technology of simple and low-cost wafer-level packaging (WLP) for thin film radio frequency (RF) devices. Low-cost practical micromachining processes were proposed as an alternative to high-cost processes, such as silicon deep reactive ion etching (DRIE) or electro-plating, in order to reduce the fabrication cost. Gold (Au)/Tin (Sn) alloy was utilized as the solder material for bonding and hermetic sealing. The small size fabricated WLP of $1.04{\times}1.04{\times}0.4mm^3$ had an average shear strength of 10.425 $kg/mm^2$, and the leakage rate of all chips was lower than $1.2{\times}10^{-5}$ atm.cc/sec. These results met Military Standards 883F (MIL-STD-883F). As the newly proposed WLP structure is simple, and its process technology is inexpensive, the fabricated WLP is a good candidate for thin film type RF devices.

• Journal of the Korean institute of surface engineering
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• v.42 no.2
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• pp.73-78
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• 2009

Quinary Ti-Al-Si-C-N films were successfully synthesized on SUS 304 substrates and Si wafers by a hybrid coating system combining an arc ion plating technique and a DC reactive magnetron sputtering technique. In this work, the effect of Si content on the microstructure and mechanical properties of Ti-Al-C-N films were systematically investigated. It was revealed that the microstructure of Ti-Al-Si-C-N coatings changed from a columnar to a nano-composite by the Si addition. Due to the nanocomposite microstructure of Ti-Al-Si-C-N coatings, the microhardness of The Ti-Al-Si-C-N coatings significantly increased up to 56 GPa. In addition the average friction coefficients of Ti-Al-Si-C-N coatings were remarkably decreased with Si addition. Therefore, Ti-Al-Si-C-N coatings can be applicable as next-generation hard-coating materials due to their improved hybrid mechanical properties.

• Journal of the Semiconductor & Display Technology
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• v.13 no.2
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• pp.29-35
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• 2014

In this study general solar cell production process was complemented, with research on improvement of solar cell efficiency through surface structure and thermal annealing process. Firstly, to form the pyramid structure, the saw damage removal (SDR) processed surface was undergone texturing process with reactive ion etching (RIE). Then, for the formation of smooth pyramid structure to facilitate uniform doping and electrode formation, the surface was etched with HND(HF : HNO3 : D.I. water=5 : 100 : 100) solution. Notably, due to uniform doping the leakage current decreased greatly. Also, for the enhancement and maintenance of minority carrier lifetime, antireflection coating thermal annealing was done. To maintain this increased lifetime, front electrode was formed through Au plating process without high temperature firing process. Through these changes in two processes, the leakage current effect could be decreased and furthermore, the conversion efficiency could be increased. Therefore, compared to the general solar cell with a conversion efficiency of 15.89%, production of high efficiency solar cell with a conversion efficiency of 17.24% was made possible.

• Korean Journal of Materials Research
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• v.5 no.8
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• pp.960-965
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• 1995

Hard Ti(C, N) layers of various compositions were coated on ASP30 tool steel employing a reactive HCD ion plating technique. The effect of film composition on the wear characteristics were investigated in lights of hardness, adhesion and wear mechanism. With an increase in the amount of nonmetallic component(N, C), the hardness of films increased, but the increase in carbon content resulted in poor adhesion. Within the concentration range of ([C+N]/Ti<1), these trends became mute clear than in the concentration below stoichiometry. Therefore, the wear resistance could be maximized when the film is deposited with the concentration of ([C+N]/Ti<1) for high microhardness and, at the same time, with the low carbon contents not to wear out in adhesive mode.

• Journal of Sensor Science and Technology
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• v.22 no.2
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• pp.130-135
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• 2013

This study proposed a noble process to fabricate TSV (Through Silicon Via) structure which has lower cost, shorter production time, and more simple fabrication process than plating method. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process. The via hole was $100{\mu}m$ in diameter and $400{\mu}m$ in depth. A dielectric layer of $SiO_2$ was formed by thermal oxidation on the front side wafer and via hole side wall. An adhesion layer of Ti and a seed layer of Au were deposited. Soldering process was applied to fill the via holes with solder paste and metal powder. When the solder paste was used as via hole metal line, sintering state and electrical properties were excellent. However, electrical connection was poor due to occurrence of many voids. In the case of metal powder, voids were reduced but sintering state and electrical properties were bad. We tried the via hole filling process by using mixing solder paste and metal powder. As a consequence, it was confirmed that mixing rate of solder paste (4) : metal powder (3) was excellent electrical characteristics.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.129-134
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• 2005

Electroplating copper is the important role in formation of 3D stacking interconnection in SiP (System in Package). The I-V characteristics curves are investigated at different electrolyte conditions. Inhibitor and accelerator are used simultaneously to investigate the effects of additives. Three different sizes of via are tested. All via were prepared with RIE (reactive ion etching) method. Via's diameter are 50, 75, $100{\mu}m$ and the height is $100{\mu}m$. Inside via, Ta was deposited for diffusion barrier and Cu was deposited fer seed layer using magnetron sputtering method. DC, pulse and pulse revere current are used in this study. With DC, via cannot be filled without defects. Pulse plating can improve the filling patterns however it cannot completely filled copper without defects. Via was filled completely without defects using pulse-reverse electroplating method.

• Korean Journal of Metals and Materials
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• v.48 no.7
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• pp.667-673
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• 2010

Copper filling into TSV (through-silicon-via) and reduction of the filling time for the three dimensional chip stacking were investigated in this study. A Si wafer with straight vias - $30\;{\mu}m$ in diameter and $60\;{\mu}m$ in depth with $200\;{\mu}m$ pitch - where the vias were drilled by DRIE (Deep Reactive Ion Etching) process, was prepared as a substrate. $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to reduce the time required complete the Cu filling into the TSV, the PPR (periodic pulse reverse) wave current was applied to the cathode of a Si chip during electroplating, and the PR (pulse-reverse) wave current was also applied for a comparison. The experimental results showed 100% filling rate into the TSV in one hour was achieved by the PPR electroplating process. At the interface between the Cu filling and Ti/ Au functional layers, no defect, such as a void, was found. Meanwhile, the electroplating by the PR current showed maximum 43% filling ratio into the TSV in an hour. The applied PPR wave form was confirmed to be effective to fill the TSV in a short time.

• Korean Journal of Metals and Materials
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• v.50 no.2
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• pp.152-158
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• 2012

The effect of current waveform on Cu filling into TSV (through-silicon via) and the bottom-up ratio of Cu were investigated for three dimensional (3D) Si chip stacking. The TSV was prepared on an Si wafer by DRIE (deep reactive ion etching); and its diameter and depth were 30 and $60{\mu}m$, respectively. $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. The current waveform was varied like a pulse, PPR (periodic pulse reverse) and 3-step PPR. As experimental results, the bottom-up ratio by the pulsed current decreased with increasing current density, and showed a value of 0.38 on average. The bottom-up ratio by the PPR current showed a value of 1.4 at a current density of $-5.85mA/cm^2$, and a value of 0.91 on average. The bottom-up ratio by the 3-step PPR current increased from 1.73 to 5.88 with time. The Cu filling by the 3-step PPR demonstrated a typical bottom-up filling, and gave a sound filling in a short time.

• Korean Journal of Metals and Materials
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• v.50 no.11
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• pp.801-808
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• 2012

TiAlCN coatings with various C contents were synthesized by unbalanced magnetron sputtering. The characteristics, the crystalline structure, surface morphology, hardness, and friction coefficient of the coatings as a function of the C content were investigated by X-ray diffraction (XRD), atomic force microscopy (AFM), a microhardness tester, and a wear test. In addition, their corrosion behaviors in a deaerated 3.5 wt% NaCl solution at $40^{\circ}C$ were investigated by potentiodynamic polarization tests. The results indicated that the $Ti_{14.9}Al_{15.5}C_{30.7}N_{38.9}$ coating had the highest hardness, elastic modulus, and a plastic deformation resistance of 39 GPa, 359 GPa, and 0.55, respectively, and it also had the lowest friction coefficient of approximately 0.26. Comparative evaluation of the TiAlCN coatings indicated that a wide range of coating properties, especially coating hardness, could be obtained by the synthesis methods and processing variables. The microhardness of the coatings was much higher than that from previously reported coating using similar magnetron sputtering processes. It was almost as high as the microhardness measured from the TiAlCN coatings (~41 GPa) synthesized using an arc ion plating process. The potentiodynamic test showed that the corrosion resistance of the TiAlCN coatings was significantly better than the TiAlN coatings, and their corrosion current density ($i_{corr}$), corrosion potentials ($E_{corr}$) and corrosion rate decreased with an increasing C content in the coatings. The much denser microstructure of the coatings due to the increased amount of amorphous phase with increasing C contents in the coatings could result in the the improved corrosion resistance of the coatings.