• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.1
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• pp.47-52
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• 2014

A simple RC circuit model of large-scale touch screen panels is developed and the frequency range of the RC model is analyzed. 2D EM simulation results of a single touch cell are cascaded for a 23 inch touch panel using a circuit simulator, and the shortest and longest channels of the full panel are modeled with a 5-element RC circuit. The 5-element RC circuit can model the touch screen panel upto 130 kHz with the channel phase error of $10^{\circ}$. 7-element RC circuit model is also proposed and the frequency range for the channel phase error of $10^{\circ}$ is extended to 200 kHz.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.209-219
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• 1995

As a new algorithm for RC tree delay estimation, we propose a $\tau$-model of the driver and a moment propagation method. The $\tau$-model represents the driver as a Thevenin equivalent circuit which has a one-time-constant voltage source and a linear resistor. The new driver model estimates the input voltage waveform applied to the RC more accurately than the k-factor model or the 2-piece waveform model. Compared with Elmore method, which is a lst-order approximation, the moment propagation method, which uses $\pi$-model loads to calculate the moments of the voltage waveform on each node of RC trees, gives more accurate results by performing higher-order approximations with the same simple tree walking algorithm. In addition, for the instability problem which is common to all the approximation methods using the moment matching technique, we propose a heuristic method which guarantees a stable and accureate 2nd order approximation. The proposed driver model and the moment propagation method give an accureacy close to SPICE results and more than 1000 times speedup over circuit level simulations for RC trees and FPGA interconnects in which the interconnect delay is dominant.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.13-26
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• 1999

This paper presents a metric that can guide to optimal circuit models for interconnects among various models, given interconnect parameters and operating environment. To get this goal, we categorize interconnects into RC~c1ass and RLC-c1ass model domains based on the quantitative modeling error analysis using total resistance, inductance and capacitance of interconnects as well as operating frequency. RC~c1ass circuit models, which include most on~chip interconnects, can be efficiently analyzed by using the model~order reduction techniques. RLC-c1ass circuit models are constructed using one of three candidates, ILC(Iterative Ladder Circuit) macromodels, MC(Method of Characteristics) macromodels, and state-based convolution method, the selection process of which is based upon the allowable modeling error and electrical parameters of interconnects. We propose the model domain diagram leading to optimal circuit models and the division of model domains has been achieved considering the simulation cost of macromodels under the environmental assumption of the general purpose circuit simulator such as SPICE. The macromodeling method presented in this paper keeps the passivity of the original interconnects and accordingly guarantees the unconditional stability of circuit models.

• Journal of the Korean Institute of Telematics and Electronics
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• v.9 no.3
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• pp.9-16
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• 1972

In this article it is shown that a GIC circuit with conversion "s" can be realized and a inductor is realized as a RC active two terminal network by using it instead of a gyrator. It is also shown that arbitary stable transfer functions can be realized as the open-circuit voltage ratio of 2 port networks which include GIC;s. In relizing the GIC circuit using transistors, it is made clear that the nullatornorator model of atransistor can be successfully applied at least in the frequency range below 10kHz. The synthesis method using GIC's is characterized with the followings; First, arbitrary stable transfer functions are realized systematically by repeating very simple network structure. Second, in the overall network all circuit elements except GICs are only resistors. Third, the number of condensers in the overall network necessary for realizing the transfer function of n-th order are n, which is believed to be the least number expected. expected.

• Journal of Electrical Engineering and Technology
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• v.13 no.3
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• pp.1147-1155
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• 2018

This paper presents an improved method to determine the internal parameters for improving accuracy of a lithium ion battery equivalent circuit model. Conventional methods for the parameter estimation directly using the curve fitting results generate the phenomenon to be incorrect due to the influence of the internal capacitive impedance. To solve this phenomenon, simple correction procedure with transient state analysis is proposed and added to the parameter estimation method. Furthermore, conventional dynamic equation for correction is enhanced with advanced RC impedance dynamic equation so that the proposed modeling results describe the battery dynamic characteristics more exactly. The improved accuracy of the battery model by the proposed modeling method is verified by single cell experiments compared to the other type of models.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.739-742
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• 2006

In this paper, we propose a method for automatic generation of equivalent circuit for unit cell of LCDTV. In order to extract a circuit model, computer program generates electrical connectivity of resistors and capacitors from the layout through pattern analysis with electrode and port information. For combining two types of independent equivalent circuits, we propose a node insertion algorithm. As a consequence, we can generate an equivalent RC circuit without increasing the capacitive elements.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.6
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• pp.91-98
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• 2004

This paper proposes a PCB plane model for generic SPICE circuit simulators. The proposed model reflects two frequency-dependent losses, namely skin and dielectric losses. After power/ground plane pair is divided into arrays of unit-cells, each unit-cell is modeled using a transmission line and two loss models. The loss model is composed of a resistor for DC loss, series HL ladder circuit for skin loss and series RC ladder circuit for dielectric loss. To verify the validity of the proposed model, it is compared with SPICE ac analysis using frequency-dependent resistors. Also, we show that the estimation results using the proposed model have a good correlation with that of VNA measurement for the typical PCB stack-up structure of general desktop PCs. With the proposed model, not only ac analysis but also transient analysis can be easily done for circuits including various non-linear/linear devices since the model consists of passive elements onl.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.83-91
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• 2000

This paper presents a new technique to reduce a large interconnect circuit with tens of thousands of elements into the one that is small enough to be analyzed by circuit simulators such as SPICE. This technique takes a fundamentally different approach form the conventional methods based on the interconnect circuit structure analysis and several rules based on the Elmore time constant. The time moments are computed form the circuit consisting of the interconnect circuit and the CMOS gate driver model computed by the AWE technique. Then, the equivalent RC circuit is synthesized from those moments. The characteristics of the driving CMOS gate can be reflected with the high degree of accuracy and the size of the compressed circuit is determined by the number of output nodes regardless of the size of the original interconnect circuits. This technique has been implemented in C language, applied to several interconnect circuits driven by a 0.5${\mu}m$ CMOS gate and the equivalent RC circuits with more than 99% reduction ratio and accuracy with 1 ~ 10% error in therms of propagation delays were obtained.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.7
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• pp.11-19
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• 1998

A signal line potential variation due to the delta-I noise was physically investigated in CMOS integrated circuits. An equivalent circuit for the noise analysis was presented. The signal line was modeled as segmented RC-lumped circuits with the ground noise. Then the equivalent circuit was mathematically analyzed. Therebvy a new signal line potential variation model due to the switching mosie was developed. Th emodel was verified with 0.35.mu.m CMOS deivce model parameters. The model has an excellent agreement with HSPICE simulation. Thus the proposed model can be dirctly employed in the industry to design the high-performance integrted circuit design as well as integrated circuit package design.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.12
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• pp.1373-1379
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• 2012

The interaction of magnetic field in the frequency range of 9~150 kHz radiating from a railway system with wireless systems has been the cause of radio frequency interference. In this paper, the equivalent circuit model of the RFI noise is proposed through source and transfer path analysis, and it is confirmed that the switching noise of several kHz that occurs a vehicle traction drive system and a substation is radiated by forming the loop circuit with a feeder line by a rolling stock. And the validity of the proposed equivalent circuit model is verified by analyzing the effects of RC banks installed in the real railway between Guri and Guksu stations, the RFI noise can be effectively mitigated by loading suitable capacitance between rail and feeding line.