Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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PCB Plane Model Including Frequency-Dependent Losses for Generic Circuit Simulators

범용 회로 시뮬레이터를 위한 손실을 반영한 PCB 평판 모형

  • 백종흠 (광운대학교 해동 ITS 기술센터) ;
  • 정용진 (광운대학교 해동 ITS 기술센터) ;
  • 김석윤 (숭실대학교 컴퓨터학부)
  • Published : 2004.06.30
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Abstract

This paper proposes a PCB plane model for generic SPICE circuit simulators. The proposed model reflects two frequency-dependent losses, namely skin and dielectric losses. After power/ground plane pair is divided into arrays of unit-cells, each unit-cell is modeled using a transmission line and two loss models. The loss model is composed of a resistor for DC loss, series HL ladder circuit for skin loss and series RC ladder circuit for dielectric loss. To verify the validity of the proposed model, it is compared with SPICE ac analysis using frequency-dependent resistors. Also, we show that the estimation results using the proposed model have a good correlation with that of VNA measurement for the typical PCB stack-up structure of general desktop PCs. With the proposed model, not only ac analysis but also transient analysis can be easily done for circuits including various non-linear/linear devices since the model consists of passive elements onl.

본 논문은 일반적인 SPICE 시뮬레이터에서 사용 가능한 PCB 평판 해석 모형을 제안한다. 제안된 모형은 주파수에 따라 증가하는 두 가지 손실, 즉, 표피 손실과 유전 손실의 영향을 반영한다. 평판은 메시(mesh) 구조로 조각을 낸 후, 각각의 단위모형은 전송선 소자와 손실 모형을 이용하여 모형화된다. 손실 모형은 DC 손실을 위해서 하나의 저항이 요구되고, 표피 손실을 위해 직렬 RL ladder 회로, 유전 손실을 위해서 직렬 RC ladder 회로가 요구된다. 제안된 모형의 검증을 위해 주파수 가변저항을 사용한 SPICE ac 해석결과를 통해 비교하고, 전형적인 데스크탑 PC용 FR4 4층 PCB 적층 구조를 만들어 VNA 측정치와도 비교할 것이다. 이 모형은 RLGC 수동 소자들로만 구성되므로 주파수 영역 및 시간 영역에서도 다양한 선형/비선형 소자들과 결합하여 과도 해석이 가능하다.

Keywords

References

  1. L. Smith, R. E. Raymond, D.W.Forehand, T.J.Pelc, T.Roy, 'Power Distribution System Design Methodology and Capacitor Selection for Modern CMOS Technology,'IEEE Transactions on Advanced Packaging, Vol.22, No. 3, pp. 284-291, August 1999 https://doi.org/10.1109/6040.784476
  2. T.Hubing, J.Drewniak, T.Van Doren, D.Hockanson, 'Power Bus Decoupling on Multilayer Printed Circuit Boards,' IEEE Transactions on Electronmagnetic Compatibility, Vol. 37, No. 2, pp. 155-166, May 1995 https://doi.org/10.1109/15.385878
  3. J. Kim, M. Swaminathan, ' Modeling of Multilayered Power Distribution Planes Using Transmission Matrix Method,' Vol.25, No. 2, pp. 189-198 May 2002 https://doi.org/10.1109/TADVP.2002.803258
  4. L. Smith, R. Raymond, and T. Roy, 'Power Plane Spice models and Simulated Performance for Materials and Geometries,' IEEE Transactions Advanced Packaging, Vol. 24, pp. 277-287, Aug. 2001 https://doi.org/10.1109/6040.938294
  5. B. Sen, R. Wheeler, ' Skin Effects Models for Transmission Line Structures using Generic SPICE Circuit Simulators,' Proc. IEEE 7th Topical Meeting on Electrical Performance of Electronic Packaging, pp. 128-131,Oct. 1998 https://doi.org/10.1109/EPEP.1998.733910
  6. G. A. Hjellen, 'Including Dielectric Loss in Printed Circuit Models for Improved EMI/EMC Predictions,' IEEE Transactions on Electromagnetic Compatibility, Vol. 39, No. 3, pp. 236-246, August 1997 https://doi.org/10.1109/15.618052
  7. I. Novak, 'Measuring Milliohms and PicoHenrys in Power Distribution Networks,' Design Con 2000
  8. Brian Young, Digital Signal Integrity Modeling and Simulation with Interconnects and Packages, Prentice-Hall, 2000, ch. 1