• Journal of IKEEE
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• v.23 no.3
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• pp.954-961
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• 2019

This paper suggests an advanced 8T SRAM which can operate properly in subthreshold voltage regime. The memory cell consists of symmetric 8 transistors, in which the latch storing data is controlled by a column-wise assistline. During the read, the data storage nodes are temporarily decoupled from the read path, thus eliminating the read disturbance. Additionally, the cell keeps the noise-vulnerable 'low' node close to the ground, thereby improving the dummy-read stability. In the write, the boosted wordline facilitates to change the contents of the memory bit. At 0.4 V supply, the advanced 8T cell achieves 65% higher dummy-read stability and 3.7 times better write-ability compared to the commercialized 8T cell. The proposed cell and circuit techniques have been verified in a 16-kbit SRAM array designed with an industrial 180-nm low-power CMOS process.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.8
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• pp.593-602
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• 2020

Power cables installed in domestic factories or underground can cause accidents depending on the manufacturing process, installation, and environmental conditions during use. When an accident occurs in a power cable, it can cause enormous economic loss and social confusion. Hence, the importance of preventive management of the cable through diagnosis is increasing to prevent it. Therefore, in this paper, a diagnostic sample cable was produced by simulating a part that could be a problem due to the installation, manufacturing defects, or deterioration of cables that can occur in the field. Dielectric loss Tangent (tan 𝛿; TD), and Partial Discharge(PD) tests were performed. Partial discharge and AC (60Hz) withstand voltage equipment using High-Frequency Current Transformer (HFCT) were applied After applying a VLF (Very Low Frequency) power supply with a frequency of 0.1Hz was applied. As a result, B and C phase defect samples at a 2.0U₀ voltage through the VLF could measure the internal partial discharge in the A-phase normal sample cable from the noise at a 0.5U₀ to 2.0U₀ voltage. In addition, the 1.5U₀ voltage was measured through the AC (60Hz) withstand voltage equipment of the commercial frequency to verify its effectiveness. Partial discharge in the run-off state was measured at a voltage of 1.0U₀, and there was a risk when installing the equipment. AC power equipment showed a difficulty of movement by volume or weight. The diagnostic method, through the VLF of the quadrant state, revealed its safety and effectiveness.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.236-244
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• 2003

In this paper, RF and IF circuits for mobile terminals which have usually been implemented using expensive BiCMOS processes are designed using CMOS circuits, and a Tx CMOS RF/IF single chip for PCS applications is designed. The designed circuit consists of an IF block including an IF PLL frequency synthesizer, an IF mixer, and a VGA and an RF block including a SSB RF mixer and a driver amplifier, and performs all transmit signal processing functions required between digital baseband and the power amplifier. The phase noise level of the designed IF PLL frequency synthesizer is -114dBc/Hz@100kHz and the lock time is less than $300{\mu}s$. It consumes 5.3mA from a 3V power supply. The conversion gain and OIP3 of the IF mixer block are 3.6dB and -11.3dBm. It consumes 5.3mA. The 3dB frequencies of the VGA are greater than 250MHz for all gain settings. The designed VGA consumes 10mA. The designed RF block exhibits a gain of 14.93dB and an OIP3 of 6.97dBm. The image and carrier suppressions are 35dBc and 31dBc, respectively. It consumes 63.4mA. The designed circuits are under fabrication using a $0.35{\mu}m$ CMOS process. The designed entire chip consumes 84mA from a 3V supply, and its area is $1.6㎜{\times}3.5㎜$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.12
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• pp.2317-2325
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• 2016

This paper presents a 10 bit successive approximation register (SAR) analog-to-digital converter (ADC) with a reference driver. The proposed SAR ADC consists of a capacitive digital-to-analog converter (CDAC), a comparator, a SAR logic, and a reference driver which improves the immunity to the power supply noise. The reference driver generates the reference voltages of 0.45 V and 1.35 V for the SAR ADC with an input voltage range of ${\pm}0.9V$. The SAR ADC is implemented using a $0.18-{\mu}m$ CMOS technology with a 1.8-V supply. The proposed SAR ADC including the reference driver almost maintains an input voltage range to be ${\pm}0.9V$ although the variation of supply voltage is +/- 200 mV. It consumes 5.32 mW at a sampling rate of 10 MS/s. The measured ENOB, DNL, and INL of the ADC are 9.11 bit, +0.60/-0.74 LSB, and +0.69/-0.65 LSB, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.5
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• pp.24-32
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• 2017

In this paper, a low power 4th order delta-sigma modulator was designed with a high resolution of 12 bits or more for the biological signal processing. Using time-interleaving technique, 4th order delta-sigma modulator was designed with one operational amplifier. So power consumption can be reduced to 1/4 than a conventional structure. To operate stably in the big difference between the two capacitor for kT/C noise and chip size, the variable-stage amplifier was designed. In the first phase and second phase, the operational amplifier is operating in a 2-stage. In the third and fourth phase, the operational amplifier is operating in a 1-stage. This was significantly improved the stability of the modulator because the phase margin exists within 60~90deg. The proposed delta-sigma modulator is designed in a standard $0.18{\mu}m$ CMOS n-well 1 poly 6 Metal technology and dissipates the power of $354{\mu}W$ with supply voltage of 1.8V. The ENOB of 11.8bit and SNDR of 72.8dB at 250Hz input frequency and 256kHz sampling frequency. From measurement results FOM1 is calculated to 49.6pJ/step and FOM2 is calculated to 154.5dB.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.7 no.6
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• pp.63-69
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• 2008

Reconfigurable RF one-chip solutions have been researched with the objective of designing for smaller-sized and more economical RF transceiver and it can be applied to a vehicular wireless terminal. The proposed voltage-controlled oscillator satisfies the targeted frequency range ($4.2{\sim}5.4\;GHz$) and the frequency planning which correspond to the standards such as CDMA(IS-95), PCS, GSM850, EGSM, WCDMA, WLAN, Bluetooth, WiBro, S-DMB, DSRC, GPS, and DVB-H/DMB-H/L(L Band). In order to improve phase noise performance, PMOS is adopted in the cross-coupled pair, the tail current source and MOS varactor in this VCO and differential-typed switching is proposed in capacitor array. Based on the measurement results, a total power dissipation is $5.3{\sim}6.0\;mW$ at 1.8 V power supply voltage. The oscillator is tuned from 4.05 to 5.62 GHz; The tuning range is 33%. The phase noise is -117.16 dBc/Hz at 1 MHz offset frequency and the FOM (Figure Of Merit) is $-180.84{\sim}-180.5$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.22-26
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• 2012

This paper introduces a 2.5-Gb/s optical receiver implemented in a standard 1P4M 0.18um CMOS technology for the applications of active optical HDMI cables. The optical receiver consists of a differential transimpedance amplifier(TIA), a five-stage differential limiting amplifier(LA), and an output buffer. The TIA exploits the inverter input configuration with a resistive feedback for low noise and power consumption. It is cascaded by an additional differential amplifier and a DC-balanced buffer to facilitate the following LA design. The LA consists of five gain cells, an output buffer, and an offset cancellation circuit. The proposed optical receiver demonstrates $91dB{\Omega}$ transimpedance gain, 1.55 GHz bandwidth even with the large photodiode capacitance of 320 fF, 16 pA/sqrt(Hz) average noise current spectral density within the bandwidth (corresponding to the optical sensitivity of -21.6 dBm for $10^{-12}$ BER), and 40 mW power dissipation from a single 1.8-V supply. Test chips occupy the area of $1.35{\times}2.46mm^2$ including pads. The optically measured eye-diagrams confirms wide and clear eye-openings for 2.5-Gb/s operations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.27-35
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• 2008

This work proposes a 14b 150MS/s 0.13um CMOS ADC for SDR systems requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC employs a calibration-free four-step pipeline architecture optimizing the scaling factor for the input trans-conductance of amplifiers and the sampling capacitance in each stage to minimize thermal noise effects and power consumption at the target resolution and sampling rate. A signal- insensitive 3-D fully symmetric layout achieves a 14b level resolution by reducing a capacitor mismatch of three MDACs. The proposed supply- and temperature- insensitive current and voltage references with on-chip RC filters minimizing the effect of switching noise are implemented with off-chip C filters. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates a measured DNL and INL within 0.81LSB and 2.83LSB, at 14b, respectively. The ADC shows a maximum SNDR of 64dB and 61dB and a maximum SFDR of 71dB and 70dB at 120MS/s and 150MS/s, respectively. The ADC with an active die area of $2.0mm^2$ consumes 140mW at 150MS/s and 1.2V.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.94-100
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• 2014

In this paper, a design of low power Current-Reuse Voltage Controlled Oscillator (VCO) which has wide tuning range about 1.95 GHz ~ 3.15 GHz is presented. Class-C type is applied to improve phase noise and 2-Step Auto Amplitude Calibration (AAC) is used for minimizing the imbalance of differential VCO output voltage which is main issue of Current-Reuse VCO. The mismatch of differential VCO output voltage is presented about 1.5mV ~ 4.5mV. This mismatch is within 0.6 % compared with VCO output voltage. Proposed Current-Reuse VCO is designed using CMOS $0.13{\mu}m$ process. Supply voltage is 1.2 V and current consumption is 2.6 mA at center frequency. The phase noise is -116.267 dBc/Hz at 2.3GHz VCO frequency at 1MHz offset. The layout size is $720{\times}580{\mu}m^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.25-33
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• 2011

This work proposes a skinny-type 10b 50MS/s 0.13um CMOS three-step pipeline ADC for CIS applications. Analog circuits for CIS applications commonly employ a high supply voltage to acquire a sufficiently acceptable dynamic range, while digital circuits use a low supply voltage to minimize power consumption. The proposed ADC converts analog signals in a wide-swing range to low voltage-based digital data using both of the two supply voltages. An op-amp sharing technique employed in residue amplifiers properly controls currents depending on the amplification mode of each pipeline stage, optimizes the performance of op-amps, and improves the power efficiency. In three FLASH ADCs, the number of input stages are reduced in half by the interpolation technique while each comparator consists of only a latch with low kick-back noise based on pull-down switches to separate the input nodes and output nodes. Reference circuits achieve a required settling time only with on-chip low-power drivers and digital correction logic has two kinds of level shifter depending on signal-voltage levels to be processed. The prototype ADC in a 0.13um CMOS to support 0.35um thick-gate-oxide transistors demonstrates the measured DNL and INL within 0.42LSB and 1.19LSB, respectively. The ADC shows a maximum SNDR of 55.4dB and a maximum SFDR of 68.7dB at 50MS/s, respectively. The ADC with an active die area of 0.53$mm^2$ consumes 15.6mW at 50MS/s with an analog voltage of 2.0V and two digital voltages of 2.8V ($=D_H$) and 1.2V ($=D_L$).