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http://dx.doi.org/10.6109/jkiice.2016.20.12.2317

A 10-bit 10-MS/s SAR ADC with a Reference Driver  

Son, Jisu (Department of Electronic Engineering, Kumoh National Institute of Technology)
Lee, Han-Yeol (Department of Electronic Engineering, Kumoh National Institute of Technology)
Kim, Yeong-Woong (Department of Electronic Engineering, Kumoh National Institute of Technology)
Jang, Young-Chan (Department of Electronic Engineering, Kumoh National Institute of Technology)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.20, no.12, 2016 , pp. 2317-2325 More about this Journal
Abstract
This paper presents a 10 bit successive approximation register (SAR) analog-to-digital converter (ADC) with a reference driver. The proposed SAR ADC consists of a capacitive digital-to-analog converter (CDAC), a comparator, a SAR logic, and a reference driver which improves the immunity to the power supply noise. The reference driver generates the reference voltages of 0.45 V and 1.35 V for the SAR ADC with an input voltage range of ${\pm}0.9V$. The SAR ADC is implemented using a $0.18-{\mu}m$ CMOS technology with a 1.8-V supply. The proposed SAR ADC including the reference driver almost maintains an input voltage range to be ${\pm}0.9V$ although the variation of supply voltage is +/- 200 mV. It consumes 5.32 mW at a sampling rate of 10 MS/s. The measured ENOB, DNL, and INL of the ADC are 9.11 bit, +0.60/-0.74 LSB, and +0.69/-0.65 LSB, respectively.
Keywords
Successive Approximation Register; Analog-To-Digital Converter; Digital-To-Analog Converter; Reference Driver;
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