• ETRI Journal
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• v.36 no.3
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• pp.352-360
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• 2014

This paper presents a 900 MHz zero-IF RF transceiver for IEEE 802.15.4g Smart Utility Networks OFDM systems. The proposed RF transceiver comprises an RF front end, a Tx baseband analog circuit, an Rx baseband analog circuit, and a ${\Delta}{\Sigma}$ fractional-N frequency synthesizer. In the RF front end, re-use of a matching network reduces the chip size of the RF transceiver. Since a T/Rx switch is implemented only at the input of the low noise amplifier, the driver amplifier can deliver its output power to an antenna without any signal loss; thus, leading to a low dc power consumption. The proposed current-driven passive mixer in Rx and voltage-mode passive mixer in Tx can mitigate the IQ crosstalk problem, while maintaining 50% duty-cycle in local oscillator clocks. The overall Rx-baseband circuits can provide a voltage gain of 70 dB with a 1 dB gain control step. The proposed RF transceiver is implemented in a $0.18{\mu}$ CMOS technology and consumes 37 mA in Tx mode and 38 mA in Rx mode from a 1.8 V supply voltage. The fabricated chip shows a Tx average power of -2 dBm, a sensitivity level of -103 dBm at 100 Kbps with PER < 1%, an Rx input $P_{1dB}$ of -11 dBm, and an Rx input IP3 of -2.3 dBm.

• Journal of Sensor Science and Technology
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• v.27 no.2
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• pp.93-98
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• 2018

In this paper, an energy-efficient 11.49-bit successive approximation register (SAR) capacitance-to-digital converter (CDC) for capacitive sensors with a figure of merit (FoM) of 31.6 pJ/conversion-step is presented. The CDC employs a SAR algorithm to obtain low power consumption and a simplified structure. The proposed circuit uses a capacitive sensing amplifier (CSA) and a dynamic latch comparator to achieve parasitic capacitance-insensitive operation. The CSA adopts a correlated double sampling (CDS) technique to reduce flicker (1/f) noise to achieve low-noise characteristics. The SAR algorithm is implemented in dual operating mode, using an 8-bit coarse programmable capacitor array in the capacitance-domain and an 8-bit R-2R digital-to-analog converter (DAC) in the charge-domain. The proposed CDC achieves a wide input capacitance range of 29.4 pF and a high resolution of 0.449 fF. The CDC is fabricated in a $0.18-{\mu}m$ 1P6M complementary metal-oxide-semiconductor (CMOS) process with an active area of 0.55 mm2. The total power consumption of the CDC is $86.4{\mu}W$ with a 1.8-V supply. The SAR CDC achieves a measured 11.49-bit resolution within a conversion time of 1.025 ms and an energy-efficiency FoM of 31.6 pJ/step.

• Journal of information and communication convergence engineering
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• v.10 no.1
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• pp.85-90
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• 2012

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

• Journal of IKEEE
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• v.18 no.2
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• pp.263-271
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• 2014

This paper presents design of the second-order sigma-delta modulator for converting voltage and temperature signals to digital ones in Battery Management IC (BMIC) for mobile applications. The second-order single-loop switched-capacitor sigma-delta modulator with 1-bit quantization in 0.13-um CMOS technology is proposed. The proposed modulator is designed using switched-opamp technique for saving power consumption. With an oversampling ratio of 256 and clock frequency of 256kHz, the modulator achieves a measured 83-dB dynamic range and a peak signal-to-(noise+distortion) ratio (SNDR) of 81.7dB. Power dissipation is about 0.66 mW at 3.3 V power supply and the occupied core area is $0.425mm^2$.

• Journal of IKEEE
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• v.22 no.4
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• pp.1218-1221
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• 2018

This paper presents a low-power 0.6-V 10-bit 200-kS/s double rail-to-rail successive approximation register (SAR) analog-to-digital converter (ADC). The proposed scheme allows input signal with 4 times power which is compared with conventional one by applying proposed rail-to-rail scheme, and that improves signal-to-noise ratio(SNR) of NTV SAR ADCs. The prototype was designed using 65-nm CMOS technology. At a 0.6-V supply and $2.4-V_{pp}$ (differential) and 200-kS/s, the ADC achieves an SNDR of 59.87 dB and consumes 364.5-nW. The ADC core occupies an active area of only $84{\times}100{\mu}m^2$.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.877-880
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• 2005

This paper describes a PLL frequency synthesizer for wireless LNA applications. The design is focused mainly on low-power and low-phase noise characteristics. A 128/129 dual-modulus prescaler has been designed using the proposed TSPC D flip-flops for high-speed operation and low-power consumption The designed synthesizer includes all building blocks for elimination of external components, other than the crystal. Its operating frequency can be programmed by external data. The frequency synthesizer has been designed using a $0.25{\mu}m$ CMOS process parameters. It operates in the frequency range of 2GHz to 3GHz and consumes 3.2mA at 2.5GHz from a 2.5V supply.

• Journal of the Korean Society for Precision Engineering
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• v.20 no.1
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• pp.99-106
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• 2003

Uninterrupted power supply has become indispensable during the maintenance task of active electric power lines as a result of today's highly information-oriented society and increasing demand of electric utilities. The maintenance task has the risk of electric shock and the danger of falling from high place. Therefore it is necessary to realize an autonomous robot system. In order to realize these tasks autonomously, the there dimensional position of target object such as electric line and the stand of insulator must be recognized accurately and rapidly. The insertion task of an electric line into a sleeve is selected as the typical task of the maintenance of active electric power distribution lines in this paper. A modified hough transform is applied to the recognition of the center of electric line and optimal target position calculation method is newly derived in order to recognize the center 3 dimensional position of the electric line. By the proposed method, it is proved that the center position of the electric line can be recognized without respect to the noise of image and the shape of electric lines and the insertion task of an electric tine is realized.

• Proceedings of the KIEE Conference
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• 1999.07f
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• pp.2650-2652
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• 1999

To satisfy the demand for small size, light weight. high density power supply, the switching frequency of DC/DC converters has been increased. The PWM control of the conventional SMPS have a switching frequency that a level of the conducted noise spectra contribute to switching frequency band. So the electronic equipment is not only affected from that but is restricted to internal regulation like CISPR, FCC, and VDE. In this paper, we analyzed Bi-FM. Bi-FM is two fixed switching frequency with a modulation frequency. So emission spectrum of Bi-FM control signal is spreaded and spectral power level is reduced. In this paper, we analyze the spectral analysis of Bi-FM control signal and the spectral comparison between the PWM control and Bi-FM control. And we confirm that reduced the spectrum power level through simulation using Pspice and experiment.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.2
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• pp.174-180
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• 2008

The pulsed amplifier which switches the main supply voltage of RF amplifier according to input pulse signal has good efficiency and low noise level between pulses. And it has simple structure because it doesn't need a pulse modulator at input port. The pulsed amplifier using the conventional switching circuit has slow fall time compared to rise time. We proposed the novel switching circuit for improving the fall time of pulsed amplifier The proposed switching circuit is implemented by replacing FET of conventional circuit with BJT. As a result of appling this circuit to RF pulsed amplifier, the rise and fall time are 5.7 ns and 21.9 ns at 27 dBm output power, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.129-131
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• 2011

An 6.4-Gb/s/channel 4-PAM transceiver is designed for a high speed memory application. The asymmetric 4-PAM signaling scheme is proposed to increase the voltage and time margins, and reduces the reference noise effect in a receiver by 33%. To reduce ISI in a channel, 1-tap pre-emphasis of a transmitter is used. The proposed asymmetric 4-PAM transceiver was implemented by using 0.13um 1-poly 6-metal CMOS process with 1.2V supply. The active area and power consumption of 1-charmel transceiver including a PLL are $0.294um^2$ and 6mW, respectively.