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저전력 31.6 pJ/step 축차 근사형 용량-디지털 직접 변환 IC

Low Power 31.6 pJ/step Successive Approximation Direct Capacitance-to-Digital Converter

  • 고영운 (충남대학교 전자공학과) ;
  • 김형섭 (충남대학교 전자공학과) ;
  • 문영진 (충남대학교 전자공학과) ;
  • 이변철 (충남대학교 전자공학과) ;
  • 고형호 (충남대학교 전자공학과)
  • Ko, Youngwoon (Department of Electronics Engineering, Chungnam National University) ;
  • Kim, Hyungsup (Department of Electronics Engineering, Chungnam National University) ;
  • Moon, Youngjin (Department of Electronics Engineering, Chungnam National University) ;
  • Lee, Byuncheol (Department of Electronics Engineering, Chungnam National University) ;
  • Ko, Hyoungho (Department of Electronics Engineering, Chungnam National University)
  • 투고 : 2017.12.26
  • 심사 : 2018.03.16
  • 발행 : 2018.03.31

초록

In this paper, an energy-efficient 11.49-bit successive approximation register (SAR) capacitance-to-digital converter (CDC) for capacitive sensors with a figure of merit (FoM) of 31.6 pJ/conversion-step is presented. The CDC employs a SAR algorithm to obtain low power consumption and a simplified structure. The proposed circuit uses a capacitive sensing amplifier (CSA) and a dynamic latch comparator to achieve parasitic capacitance-insensitive operation. The CSA adopts a correlated double sampling (CDS) technique to reduce flicker (1/f) noise to achieve low-noise characteristics. The SAR algorithm is implemented in dual operating mode, using an 8-bit coarse programmable capacitor array in the capacitance-domain and an 8-bit R-2R digital-to-analog converter (DAC) in the charge-domain. The proposed CDC achieves a wide input capacitance range of 29.4 pF and a high resolution of 0.449 fF. The CDC is fabricated in a $0.18-{\mu}m$ 1P6M complementary metal-oxide-semiconductor (CMOS) process with an active area of 0.55 mm2. The total power consumption of the CDC is $86.4{\mu}W$ with a 1.8-V supply. The SAR CDC achieves a measured 11.49-bit resolution within a conversion time of 1.025 ms and an energy-efficiency FoM of 31.6 pJ/step.

키워드

참고문헌

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