• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(5)
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• pp.189-192
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• 2001

A new configuration of acoustic echo canceler with stepsize predictor and comparator is proposed in this paper. Conventional acoustic echo cancelers using ES(Exponential Step)algorithm has fast convergence speed, but very weak in interference of environment. The proposed stepsize predictor and comparator improve conventional acoustic echo canceler's defects. The Stepsize predictor generates a stepsize value using residual power of error signal. The stepsize comparator selects the stepsize value that is better performance in a acoustic echo canceler using a stepsize decision factor. The Simulation results show superiority of the proposed acoustic echo canceler in environment interference.

• 한국전기전자재료학회논문지
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• 제21권5호
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• pp.421-425
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• 2008

In this research, a 8-bit CMOS 2 stage folding A/D converter is designed, For low power consumption and small chip size, the A/D converter is designed by using folding and interpolation circuit. Folding circuit is composed of the transistor differential pairs which are connected in parallel. It reduces the number of comparator drastically. The analog block composed of folding block, current interpolation circuit, and three stage current comparator is designed with differential-mode for high speed operation. The simulation in a $0.35\;{\mu}m$ CMOS process. shows DNL and SNDR of 0.5LSB and 47 dB at 250 MHz/s sampling frequency.

• IEIE Transactions on Smart Processing and Computing
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• 제4권3호
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• pp.183-188
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• 2015

A 10-bit 10MS/s low power consumption successive approximation register (SAR) analog-to-digital converter (ADC) using a straightforward capacitive digital-to-analog converter (DAC) is presented in this paper. In the proposed capacitive DAC, switching is always straightforward, and its value is half of the peak-to-peak voltage in each step. Also the most significant bit (MSB) is decided without any switching power consumption. The application of the straightforward switching causes lower power consumption in the structure. The input is sampled at the bottom plate of the capacitor digital-to-analog converter (CDAC) as it provides better linearity and a higher effective number of bits. The comparator applies adaptive power control, which reduces the overall power consumption. The differential prototype SAR ADC was implemented with $0.18{\mu}m$ complementary metal-oxide semiconductor (CMOS) technology and achieves an effective number of bits (ENOB) of 9.49 at a sampling frequency of 10MS/s. The structure consumes 0.522mW from a 1.8V supply. Signal to noise-plus-distortion ratio (SNDR) and spurious free dynamic range (SFDR) are 59.5 dB and 67.1 dB and the figure of merit (FOM) is 95 fJ/conversion-step.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제55권5호
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• pp.250-256
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• 2006

Both ratio error and phase angle error in current transformer(CT) depend critically on values of CT burden. Thus, precise measurement of CT burden is very important for the evaluation of CT. A method for the measurement of CT burden has been developed by employing the portable shunt precise resistor with negligible AC-DC resistance difference less than $10^{-5}$. The burden value(value and power factor) can be calculated from resistance and reactance obtained by measuring the change of ratio error and phase angle error caused by the change of shunt resistor. The uncertainty for the method is evaluated and found to be abut 2 %.

• 대한전자공학회논문지SD
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• 제41권4호
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• pp.67-74
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• 2004

기존의 버스트 모드 자동전력제어 회로는 데이터 율이 증가함에 따라 마크밀도 변화 영향을 심하게 받아 에러를 야기하였다. 이 문제를 해결하기 위해 높은 데이터 율에서도 마크밀도의 영향을 배제시킬 수 있는 새로운 구조의 첨두 비교기를 고안하고 이를 자동전력제어 회로에 적용하여 마크밀도 변화에 강한 버스트 모드 자동전력제어 회로를 제안하였다. 제안한 자동전력제어 회로 내의 첨두 비교기는 높은 데이터 율에서 뿐만 아니라 광범위한 기준전류 및 차 전류 변화에서도 미소한 마크밀도 변화 영향만을 보여 마크밀도 변화에 매우 강한 특성을 확인 할 수 있었다.

• 전자공학회논문지SC
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• 제37권2호
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• pp.37-42
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• 2000

본 논문에서는 파이프라인드 구조의 빠른 변환 속도와 축차비교 구조의 저전력 구조를 이용하여 고속, 저전력 아날로그 디지털 변환기를 제안하였다. 제안된 구조의 변환 방법은 축차비교 구조의 변환에서 비교기를 파이프라인드 구조로 연결하여 홀드된 주기에 비교기의 기준 전위를 전 비교기의 출력 값에 의해 변환하도록 하여 고속 동작이 가능하도록 하였다. 제안된 구조에 의해 8비트 아날로그 디지털 변환기를 0.8㎛ CMOS공정으로 HSPICE를 이용하여 시뮬레이션한 결과, INL/DNL(Integral Non-Linearity/Differential Non-Linearity)은 각각 ±0.5/±1이었으며, 100㎑ 사인 입력 신호를 10MS/s로 샘플링 하여 DFT(Discrete Fourier Transform)측정 결과 SNR(Signal to Noise Ratio)은 41㏈를 얻을 수 있었다. 10MS/s의 변환 속도에서 전력 소모는 4.14㎽로 측정되었다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2000년도 전력전자학술대회 논문집
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• pp.384-387
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• 2000

In this paper Power factor correction circuit of single-phase three-level boost converter is proposed. The advantage of the proposed control scheme for three-level boost converter are low blocking voltage of each power device low THD(Total Harmonic Distortion) and high power factor. The control scheme is based on the current comparator capacitor compensator and region detector, In simulations the proposed system is validated.

• 한국산업정보학회논문지
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• 제20권1호
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• pp.1-7
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• 2015

In this paper, a 12-bit high resolution, power and area efficiency hybrid digital pulse width modulator (DPWM) with process and temperature (PT) calibration has been proposed for digital controlled DC-DC converters. The hybrid structure of DPWM combines a 6-bit differential tapped delay line ring-mux digital-to-time converter (DTC) schema and a 6-bit counter-comparator DTC schema, resulting in a power and area saving solution. Furthermore, since the 6-bit differential delay line ring oscillator serves as the clock to the high 6-bit counter-comparator DTC, a high frequency clock is eliminated, and the power is significantly saved. In order to have a simple delay cell and flexible delay time controllability, a voltage controlled inverter is adopted to build the deferential delay cell, which allows fine-tuning of the delay time. The PT calibration circuit is composed of process and temperature monitors, two 2-bit flash ADCs and a lookup table. The monitor circuits sense the PT (Process and Temperature) variations, and the flash ADC converts the data into a digital code. The complete circuits design has been verified under different corners of CMOS 0.18um process technology node.

• 한국통신학회논문지
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• 제19권3호
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• pp.582-590
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• 1994

전력선 통신을 위한 간단하면서 융통성이 큰 2-반송과 DS방식의 데이터 전송모뎀을 구현하고, 그 특성을 해석적으로 검토하였으며 실험을 통해 이것을 확인 하였다. 제안된 시스템은 DS모뎀 출력에 극성에 따라 독립된 2개의 반송파 주파수를 할당하여 전송케 하므로서 완전한 DSSS 동작을 보장 하도록 한다. 수신단말기의 두 포락선 검파출력은 재래방식 처리 비교기에 입력되지 않고 먼저 DS 상관기에 입력시켜서 그 출력을 잡음과 비교판정 하게 된다. 이때, 역확산되어 약화된 잡음전략이 신호와 비교되기 때문에 데이터의 에러율은 현저하게 개선 된다. 이 시스템은 구성이 비교적 간단함에도 불구하고, 2400bps의 데이터를 전송 할때, 재래식의 FSK 방식에 비하여 10dB정도 더 높은 선로잡음아래에서도 에러율 10 정도를 유지할 수가 있다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2003년도 춘계전력전자학술대회 논문집(2)
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• pp.812-815
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• 2003

Most of all, DTC drive is very simple in its implementation because it needs only two hysteresis comparator and switching vector table for both flux and torque control. The switching strategy of a conventional direct torque control scheme which is based on hysteresis comparator results in a variable switching frequency which depends on the speed, flux, stator voltage and the hysteresis of the comparator. The amplitude of hysteresis band greatly influences on the drive performance such as flux and torque ripple and inverter switching frequency. In this paper the influence of the amplitudes of flux and torque hysteresis bands and sampling time of control program on the torque and flux ripples are investigated. Simulation results confirm the superiority of the DTC under the proposed method over the conventional DTC.