IEIE Transactions on Smart Processing and Computing

The Institute of Electronics and Information Engineers (대한전자공학회)
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A 10-bit 10MS/s differential straightforward SAR ADC

  • Rikan, Behnam Samadpoor (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Abbasizadeh, Hamed (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Lee, Dong-Soo (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Lee, Kang-Yoon (College of Information and Communication Engineering, Sungkyunkwan University)
  • Received : 2015.04.29
  • Accepted : 2015.06.15
  • Published : 2015.06.30
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Abstract

A 10-bit 10MS/s low power consumption successive approximation register (SAR) analog-to-digital converter (ADC) using a straightforward capacitive digital-to-analog converter (DAC) is presented in this paper. In the proposed capacitive DAC, switching is always straightforward, and its value is half of the peak-to-peak voltage in each step. Also the most significant bit (MSB) is decided without any switching power consumption. The application of the straightforward switching causes lower power consumption in the structure. The input is sampled at the bottom plate of the capacitor digital-to-analog converter (CDAC) as it provides better linearity and a higher effective number of bits. The comparator applies adaptive power control, which reduces the overall power consumption. The differential prototype SAR ADC was implemented with $0.18{\mu}m$ complementary metal-oxide semiconductor (CMOS) technology and achieves an effective number of bits (ENOB) of 9.49 at a sampling frequency of 10MS/s. The structure consumes 0.522mW from a 1.8V supply. Signal to noise-plus-distortion ratio (SNDR) and spurious free dynamic range (SFDR) are 59.5 dB and 67.1 dB and the figure of merit (FOM) is 95 fJ/conversion-step.

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References

  1. B. G. Lee and S. G. Lee, "Input-tracking DAC for low-power high-linearity SAR ADC," Electronic Letters, Aug. 2011.
  2. C. Yuan and Y. Lam, "Low-energy and area-efficient tri-level switching scheme for SAR ADC," Electronic Letters, Apr. 2012.
  3. B. Kim, L. Yan, J. Yoo, N. Cho and H-J Yoo, "An Energy-Efficient Dual Sampling SAR ADC with Reduced Capacitive DAC," Circuits and Systems, ISCAS. IEEE International Symposium, 2009.
  4. J. Lin, W. Yu and G.C. Temes, "Multi-step capacitorsplitting SAR ADC," Electronic Letters, Oct. 2010.
  5. P. W. LI, M. J. Chin, P. R. Gray and R. Castello, "A Ratio-Independent Algorithmic Analog-to-Digital Conversion Technique," IEEE Journal of Solid-State Circuits, VOL. SC-19, NO.6, Dec. 1984.
  6. Y. M. Kim, J. S. Park, Y. J. Shin and S. H. Lee, "An 87 fJ/conversion-step 12 b 10 MS/s SAR ADC using a minimum number of unit capacitors," Analog Integr Circ Sig Process, 2014.
  7. C. H. Chan, Y. Zhu, U. F. Chio, S. W. Sin, S. P. U, R. P. Martins, "A Reconfigurable Low-Noise Dynamic Comparator with Offset Calibration in 90nm CMOS," IEEE Asian Solid-State Circuits Conference, Nov. 2011.
  8. M. Miyahara, Y. Asada, D. Paik and A. Matsuzawa, "A Low-Noise Self-Calibrating Dynamic Comparator for High-Speed ADCs," IEEE Asian Solid-State Circuits Conference, Nov. 2008.
  9. C. Y. Li, C. W. Lu, H. T. Chao and C. Hsia, "A 10-Bit Area-Efficient SAR ADC with Re-usable Capacitive Array," IEEE International Conference on Anti-Counterfeiting, Security and Identification (ASID), 2012.
  10. C. C. Lu, "A 1.2V 10-bit 5 MS/s CMOS Cyclic ADC," IEEE International Symposium on Circuits and Systems (ISCAS), 2013.