• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.32 no.3
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• pp.201-206
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• 2019

This report constitutes the first demonstration in Korea of single-crystal lateral gallium oxide ($Ga_2O_3$) as a metal-oxide-semiconductor field-effect-transistor (MOSFET), with a breakdown voltage in excess of 480 V. A Si-doped channel layer was grown on a Fe-doped semi-insulating ${\beta}-Ga_2O_3$ (010) substrate by molecular beam epitaxy. The single-crystal substrate was grown by the edge-defined film-fed growth method and wafered to a size of $10{\times}15mm^2$. Although we fabricated several types of power devices using the same process, we only report the characterization of a finger-type MOSFET with a gate length ($L_g$) of $2{\mu}m$ and a gate-drain spacing ($L_{gd}$) of $5{\mu}m$. The MOSFET showed a favorable drain current modulation according to the gate voltage swing. A complete drain current pinch-off feature was also obtained for $V_{gs}<-6V$, and the three-terminal off-state breakdown voltage was over 482 V in a $L_{gd}=5{\mu}m$ device measured in Fluorinert ambient at $V_{gs}=-10V$. A low drain leakage current of 4.7 nA at the off-state led to a high on/off drain current ratio of approximately $5.3{\times}10^5$. These device characteristics indicate the promising potential of $Ga_2O_3$-based electrical devices for next-generation high-power device applications, such as electrical autonomous vehicles, railroads, photovoltaics, renewable energy, and industry.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.43-52
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• 2005

An prescaler which uses PLL(Phase Locked Loop) must satisfy high speed operation and low power consumption. Thus the performance or TSPC(True Single Phase Clocked) D-flip flops which is applied at Prescaler is very important. Power consumption of conventional TSPC D-flip flops was increased with glitches from output and unnecessary discharge at internal node in precharge phase. We proposed a new D-flip flop which reduced two clock transistors for precharge and discharge Phase. With inserting a new PMOS transistor to the input stage, we could prevent from unnecessary discharge in precharge phase. Moreover, to remove the glitch problems at output, we inserted an PMOS transistor in output stage. The proposed flip flop showed stable operations as well as low power consumption. The maximum frequency of prescaler by applying the proposed D-flip flop was 2.92GHz and achieved power consumption of 10.61mw at 3.3V. In comparison with prescaler applying the conventional TSPC D-flip $flop^[6]$, we obtained the performance improvement of $45.4\%$ in the view of PDP(Power-Belay-Product).

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.591-600
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• 2010

In this paper, three kinds of 24 GHz low-power CMOS cross-coupled voltage controlled oscillators are designed and fabricated for a short-range radar applications using TSMC 0.13 ${\mu}m$ CMOS process. The basic CMOS crosscoupled voltage controlled oscillator is designed for oscillating around a center frequency of 24.1 GHz and subthreshold oscillators are developed for low power operation from it. A double resonant circuit is newly applied to the subthreshold oscillator to improve the problem that parasitic capacitance of large transistors in a subthreshold oscillator can push the oscillation frequency toward lower frequencies. The fabricated chips show the phase noise of -101~-103.5 dBc/Hz at 1 MHz offset, the output power of -11.85~-15.33 dBm and the frequency tuning range of 475~852 MHz. In terms of power consumption, the basic oscillator consumes 5.6 mW, while the subthreshold oscillator does 3.3 mW. The subthreshold oscillator with the double resonant circuit shows relatively lower power consumption and improved phase noise performance while maintaining a comparable frequency tuning range. The subthreshold oscillator with double resonances has FOM of -185.2 dBc based on 1 mW DC power reference, which is an about 3 dB improved result compared with the basic oscillator.

• Korean Journal of Materials Research
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• v.14 no.8
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• pp.542-546
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• 2004

We report a new fabrication process for high performance triode type CNT field emitters and their superior electrical properties. The CNT-based triode-type field emitter structure was fabricated by the conventional semiconductor processes. The keys of the fabrication process are spin-on-glass coating and trim-and-leveling of the carbon nanotubes grown in trench structures by employing a chemical mechanical polishing process. They lead to strong adhesion and a uniform distance from the carbon nanotube tips to the electrode. The measured emission property of the arrays showed a remarkably uniform and high current density. The gate leakage current could be remarkably reduced by coating of thin $SiO_{2}$ insulating layer over the gate metal. The field enhancement factor(${\beta}$) and emission area(${\alpha}$) were calculated from the F-N plot. This process can be applicable to fabrication of high power CNT vacuum transistors with good electrical performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.28-33
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• 2007

The front-end system having a capable of 2x reading and writing of BD-R/Ra/ROM is developed. Its readability is improved by adopting 5-tap adaptive partial response maximum likelihood (PRML) with the PR(a,b,c,d,e) type channel. Due to the proposed PRML, less than $2{\times}10^{-4}$ of the bit error rate (BER) is achieved with radial and tangential tilt margin of over${\mp}0.6{\circ}$ on 25GB disc in 2x speed. The method of an optimum Power control (OPC) for stable writing of various BD-R/RE is proposed. The developed chip contains 14-million transistors in a $60mm^2$ dies, and is fabricated in $0.18-{\mu}m$ CMOS technology.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.209.1-209.1
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• 2015

Indium gallium zinc oxide (IGZO), indium zinc oxide (IZO) 그리고 zinc tin oxide (ZTO) 같은 zinc oxide 기반의 산화물 반도체는 높은 이동도, 투과도 그리고 유연성 같은 장점을 갖고 있어, display application의 backplane 소자로 적용되고 있다. 또한 최근에는 산화물 반도체를 이용한 thin-film transistor (TFT) 뿐만아니라 resistive random access memory (RRAM), flash memory 그리고 pH 센서 등 다양한 반도체 소자에 적용을 위한 연구가 활발히 진행 중이다. 그러나 zinc oxide 기반의 산화물 반도체의 전기 화학적 불안정성은 위와 같은 소자에 적용하는데 제약이 있다. 산화물 반도체의 안정성에 영향을 미치는 다양한 요인들 중 한 가지는, sputter 같은 plasma를 이용한 공정 진행 시 active layer가 plasma에 노출되면서 threshold voltage (Vth)가 급격하게 변화하는 plasma damage effect 이다. 급격한 Vth의 변화는 동작 전압의 불안정성을 가져옴과 동시에 누설전류를 증가시키는 결과를 초래 한다. 따라서 본 연구에서는, IGZO 기반의 TFT를 제작 후 plasma 분위기에 노출시켜, power와 노출 시간에 따른 전기적 특성 변화를 확인 하였다. 또한, thermal annealing을 적용하여 열처리 온도와 시간에 따른 Vth의 회복특성을 조사 하였다. 이러한 결과는 추후 산화물 반도체를 이용한 다양한 소자 설계 시 유용할 것으로 기대된다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.5
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• pp.270-275
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• 2017

Current progress in the development of semiconductor technology in applications involving high electron mobility transistors (HEMT) and power devices is hindered by the lack of adequate ways todissipate heat generated during device operation. Concurrently, electronic devices that use gallium nitride (GaN) substrates do not perform well, because of the poor heat dissipation of the substrate. Suggested alternatives for overcoming these limitations include integration of high thermal conductivity material like diamond near the active device areas. This study will address a critical development in the art of GaN on diamond (GOD) structure by designing for ideal heat dissipation, in order to create apathway with the least thermal resistance and to improve the overall ease of integrating diamond heat spreaders into future electronic devices. This research has been carried out by means of heat transfer simulation, which has been successfully demonstrated by a finite-element method.

• Smart Structures and Systems
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• v.8 no.1
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• pp.39-52
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• 2011

We are developing a biomimetic robot based on the Sea Lamprey. The robot consists of a cylindrical electronics bay propelled by an undulatory body axis. Shape memory alloy (SMA) actuators generate propagating flexion waves in five undulatory segments of a polyurethane strip. The behavior of the robot is controlled by an electronic nervous system (ENS) composed of networks of discrete-time map-based neurons and synapses that execute on a digital signal processing chip. Motor neuron action potentials gate power transistors that apply current to the SMA actuators. The ENS consists of a set of segmental central pattern generators (CPGs), modulated by layered command and coordinating neuron networks, that integrate input from exteroceptive sensors including a compass, accelerometers, inclinometers and a short baseline sonar array (SBA). The CPGs instantiate the 3-element hemi-segmental network model established from physiological studies. Anterior and posterior propagating pathways between CPGs mediate intersegmental coordination to generate flexion waves for forward and backward swimming. The command network mediates layered exteroceptive reflexes for homing, primary orientation, and impediment compensation. The SBA allows homing on a sonar beacon by indicating deviations in azimuth and inclination. Inclinometers actuate a bending segment between the hull and undulator to allow climb and dive. Accelerometers can distinguish collisions from impediment to allow compensatory reflexes. Modulatory commands mediate speed control and turning. A SBA communications interface is being developed to allow supervised reactive autonomy.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.3
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• pp.99-104
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• 2002

lateral insulated gate bipolar transistors(LIGBTs) are extensively used in high voltage power IC application due to their low forward voltage drops. One of the main disadvantages of the LIGBT is its scow switching speed when compared to the LDMOSFET. And the LIGBT with reverse channel structure is lower current capability than the conventional LIGBT at the forward conduction mode. In this paper, the LIGBT which included p+ ring and p-channel gate is presented at the reverie channel structure. The presented LIGBT structure is proposed to suppress the latch up, efficiently and to improve the turn off time. It is shown to improve the current capability too. It is verified 2-D simulator, MEDICI. It is shown that the latch up current of new LIGBT is 10 times than that of the conventional LIGBT Additionally, it is shown that the turn off characteristics of the proposed LIGBT is i times than that of the conventional LIGBT. It is net presented the tail current of turn off characteristics at the proposed structure. And the presented LIGBT is not n+ buffer layer because it includes p channel gate and p+ ring.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.212-214
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• 2005

The charge-pump circuit which is used to generate higher voltage than the available supply voltage has wide applications such as the flash memory of EEPROM Because the demand for high voltage comes from physical mechanism such as the oxide tunneling, the required pumped voltage cannot be scaled as the power supply voltage is scaled. Therefore, an efficient charge-pump circuit that can achieve high voltage from the available low supply voltage is essential. A new Analog Switch p-well CMOS charge pump circuit without the MOS device body effect is processed. By improve the structure of the circuit's transistors to reduce the threshold voltage shift of the devices, the threshold voltage of the device is kept constant. So, the circuit electrical characteristics are higher output voltage within a shorter time than the conventional charge pump. The propose analog switch CMOS charge pump shows compatible performance of the ideal diode or Dickson charge pump.