• 전자공학회논문지C
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• 제36C권11호
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• pp.10-17
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• 1999

본 논문에서는 MOS 트랜지스터로만 이루어진 CMOS IADC(Current-mode Analog-to-Digital Converter)를 설계하였다. 각 단은 CSH(Current Sample-and-Hold)와 CCMP(Current Comparator)로 구성된 1.5-비트 비트 셀로 구성되었다. 비트 셀 전단은 CFT(Clock Feedthrough)가 제거된 9-비트 해상도의 차동 CSH를 배치하였고, 각 단 비트 셀의 ADSC(Analog-to-Digital Subconverter)는 2개의 래치 CCMP로 구성되었다. 제안된 IADC를 현대 0.65 ㎛ CMOS 파라미터로 ACAD 시뮬레이션 한 결과, 20 Ms/s에서 100 ㎑의 입력 신호에 대한 SINAD(Signal to Noise-Plus-Distortion)은 47 ㏈ SNR (Signal-to-Noise)는 50 ㏈(8-bit)을 얻었고 35.7 ㎽ 소비전력 특성을 나타냈다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권3호
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• pp.145-152
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• 2003

Electrical gate and drain characteristics of double heterostructure InAlAs/InGaAs pseudomorphic HEMTs have been investigated under sub-bandgap photonic excitation ($hv). Drain $(V_{DS})-,{\;}gate($V_{DS})-$, and optical power($P_{opt}$)-dependent variation of the abnormal gate leakage current and associated physical mechanisms in the PHEMTs have been characterized. Peak gate voltage ($V_{GS,P}$) and the onset voltage for the impact ionization ($V_{GS.II}$) have been extracted and empirical model for their dependence on the $V_{DS}$ and $P_{opt} have been proposed. Anomalous gate and drain current, both under dark and under sub-bandgap photonic excitation, have been modeled as a parallel connection of high performance PHEMT with a poor satellite FET as a parasitic channel. Sub-bandgap photonic characterization, as a function of the optical power with $h\nu=0.799eV$, has been comparatively combined with those under dark condition for characterizing the bell-shaped negative humps in the gate current and subthreshold drain leakage under a large drain bias.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 춘계학술대회 논문집 유기절연재료 전자세라믹 방전플라즈마 일렉트렛트 및 응용기술
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• pp.15-17
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• 2002

Leakage inductance and temperature rise are two of the more impotent problems facing the magnetic core technology of today's high frequency transformers. Excessive leakage inductance increases the stress on the switching transistors and limits the duty-cycle, and excessive temperature rise can lead the design limitation of high frequency transformer with high current. The flat transformer technology provides a very good solution to the problems of leakage inductance and thermal management for high frequency power. The critical magnetic components and windings are optimized and packaged within a completely assembled module. The turns ratio in a flat transformer is determined as the product of the number of elements or modules times the number of primary turns. The leakage inductance increase proportionately to the number of elements, but since it is reduced as the square of the turns, the net reduction can be very significant. The flat transformer modules use cores which have no gap. This eliminates fringing fluxes and stray flux outside of the core. The secondary windings are formed of flat metal and are bonded to the inside surface of the core. The secondary winding thus surrounds the primary winding, so nearly all of the flux is captured.

• Journal of Electrical Engineering and Technology
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• 제7권1호
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• pp.81-85
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• 2012

This paper presents a wideband and low-noise direct conversion front-end receiver supporting VHF and UHFbands simultaneously. The receiver iscomposed of a low-noise amplifier (LNA), a down conversion quadrature mixer, and a frequency divider by 2. The cascode configuration with the resistor feedback is exploited in the LNA to achieve a wide operating bandwidth. Four gainstep modesare employed using a switched resistor bank and a capacitor bank in the signal path to cope with wide dynamic input power range. The verticalbipolar junction transistors are used as the switching elements in the mixer to reduce 1/f noise corner frequency. The proposed front-end receiver fabricated in 0.18 ${\mu}m$ CMOS technology shows very low minimum noise figureof 1.8 dB and third order input intercept pointof -12dBm inthe high-gain mode of 26.5 dBmeasured at 500 MHz.The proposed receiverconsumeslow current of 20 mA from a 1.8 V power supply.

• 한국전기전자재료학회논문지
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• 제24권9호
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• pp.693-696
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• 2011

Recently, amorphous oxide semiconductors (AOSs) based thin-film transistors (TFTs) have received considerable attention for application in the next generation displays industry. The research trends of AOSs based TFTs investigation have focused on the high device performance. The electrical properties of the TFTs are influenced by trap density. In particular, the threshold voltage ($V_{th}$) and subthreshold swing (SS) essentially depend on the semiconductor/gate-insulator interface trap. In this article, we investigated the effects of Ar plasma-treated $SiO_2$ insulator on the interfacial property and the device performances of amorphous indium gallium zinc oxide (a-IGZO) TFTs. We report on the improvement in interfacial characteristics between a-IGZO channel layer and gate insulator depending on Ar power in plasma process, since the change of treatment power could result in different plasma damage on the interface.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 하계학술대회 논문집 B
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• pp.1238-1240
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• 2003

A new soft switching technique that improves performance of the high power factor boost rectifier by reducing switching losses is introduced. The losses are reduced by air active snubber which consists of an inductor, a capacitor a rectifier, and an auxiliary switch. Since the boost switch turns off with zero current, this technique is well suited for implementations with insulated gate bipolar transistors. The reverse recovery related losses of the rectifier are also reduced by the snubber inductor which is connected in series with the boost switch and the boost rectifier. In addition, the auxiliary switch operates with zero voltage switching. A complete design procedure and extensive performance evaluation of the proposed active snubber using a 1.2[kW] high power factor boost rectifier operating from a 90 [$V_{rms}$] input are also presented.

• Transactions on Electrical and Electronic Materials
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• 제18권4호
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• pp.229-236
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• 2017

This paper deals with the design and implementation of an efficient topology for cascaded multilevel inverters with reduced part counts. In the proposed design, a well-established basic unit is first developed. The series extension of this unit results in the formation of the proposed multilevel inverter. The proposed design minimizes the number of power electronic components including insulated-gate bipolar transistors and gate driver circuits, which in turn cuts down the size of the inverter assembly and reduces the operating power losses. An explicit control strategy with enhanced device efficiency is also acquired. Thus, the part count reductions enhance not only the economical merits but also the technical features of the entire system. In order to accomplish the desired operational aspects, three algorithms are considered to determine the magnitudes of the dc voltage sources effectively. The proposed topology is compared with the conventional cascaded H-bridge multilevel inverter topology, to reflect the merits of the presented structure. In continue, both the analytical and experimental results of a cascaded 31-level structure are analyzed. The obtained results are discussed in depth, and the exemplary performance of the proposed structure is corroborated.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 추계학술대회 논문집 Vol.16
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• pp.587-590
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• 2003

The first attention in designing a transformer for low temperature rise should be to reduce losses. Leakage inductance and temperature rise are two of the more impotent problems facing the magnetic core technology of today's high frequency transformers. Excessive leakage inductance increases the stress on the switching transistors and limits the duty-cycle, and excessive temperature rise can lead the design limitation of high frequency transformer with high current. The flat transformer technology provides a very good solution to the problems of leakage inductance and thermal management for high frequency power. The critical magnetic components and windings are optimized and packaged within a completely assembled module. The turns ratio in a flat transformer is determined as the product of the number of elements or modules times the number of primary turns. The leakage inductance increase proportionately to the number of elements, but since it is reduced as the square of the turns, the net reduction can be very significant. The flat transformer modules use cores which have no gap. This eliminates fringing fluxes and stray flux outside of the core. The secondary windings are formed of flat metal and are bonded to the inside surface of the core. The secondary winding thus surrounds the primary winding, so nearly all of the flux is captured.

• 한국재료학회지
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• 제18권10호
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• pp.552-556
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• 2008

Modified thermal annealing was applied to the activation of the polycrystalline silicon films doped as p-type through implantation of $B_2H_6$. The statistical design of experiments was successfully employed to investigate the effect of rapid thermal annealing on activation of polycrystalline Si doped as p-type. In this design, the input variables are furnace temperature, power of halogen lamps, and alternating magnetic field. The degree of ion activation was evaluated as a function of processing variables, using Hall effect measurements and Raman spectroscopy. The main effects were estimated to be furnace temperature and RTA power in increasing conductivity, explained by recrystallization of doped ions and change of an amorphous Si into a crystalline Si lattice. The ion activation using rapid thermal annealing is proven to be a highly efficient process in low temperature polycrystalline Si technology.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 D
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• pp.1818-1820
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• 1999

This paper presents direct ${\mu}c$-Si:H thin film growth on the glass substrates using RPCVD system (remote plasma chemical vapor deposition) in low temperature. Hydrogenated micro-crystalline silicon deposited by RPCVD system in low temperature is very useful material for photovoltaic devices, sensor applications, and TFTs (thin film transistors). Varying the deposition conditions such as substrate temperature, gas flow rate, reactive gas ratio $(SiH_4/H_2)$, total chamber pressure, and rf power, we deposited ${\mu}c$-Si:H thin films on the glass substrates (Corning glass 1737). And then we measured the structural and electrical properties of the films.