• Journal of the Korean Vacuum Society
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• v.8 no.3A
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• pp.238-244
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• 1999

Pt/SBT/Pt capacitors were fabricated using the MOD-derived $SrBi_{2x}Ta_2O_9$ (SBT) films and their ferroelectic and leakage current characteristics were investigated with post annealing at 400~$800^{\circ}C$. Although the MOD-derived SBT film exhibited the hysteresis loop typical for the leaky film, the well-saturated ferroelectric hysteresis loop could be obtained by post annealing the Pt/SBT/Pt capacitors at $550^{\circ}C$~$800^{\circ}C$. The remanent polarization $2P_r$ of the SBT film exhibited a maximum value of 9.72$\mu\textrm{cm}^2$ with post annealing at $600^{\circ}C$, and then decreased with increasing the post annealing temperature above $600^{\circ}C$. The MOD-derived SBT films exhibited the high leakage current density of ~$10^{-3} \textrm{A/cm}^2$ at 75kV/cm. With post annealing the Pt/SBT/Pt capacitor at 600~$800^{\circ}C$, however, the leakage current density decreased remarkably to less than $10^{-6}\textrm{A/cm}^2$ at 75kV/cm.

• Transactions on Electrical and Electronic Materials
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• v.15 no.2
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• pp.73-76
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• 2014

$Pt/Al_2O_3/La_2Si_5O_x/SiO_2/Si$ charge trap memory capacitors were prepared, in which the $La_2Si_5O_x$ film was used as the charge trapping layer, and the effects of post annealing atmospheres ($NH_3$ and $N_2$) on their memory characteristics were investigated. $La_2O_3$ nanocrystallites, as the storage nodes, precipitated from the amorphous $La_2Si_5O_x$ film during rapid thermal annealing. The $NH_3$ annealed memory capacitor showed higher charge storage performances than either the capacitor without annealing or the capacitor annealed in $N_2$. The memory characteristics were enhanced because more nitrogen was incorporated at the $La_2Si_5O_x/SiO_2$ interface and interfacial reaction was suppressed after the $NH_3$ annealing treatment.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.709-712
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• 2001

The effects of post annealing temperature by the Rapid Thermal Annealing(RTA) on the electrical properties of Pb(Zr,Ti)O$_3$(PZT) thin film were investigated. Analyses by the RTA treatments reveled that the leakage current of PZT thin films strongly depend on heating temperature and time. It was found that leakage current properties of PZT capacitor were changed by heating temperature during the RTA annealing. On Pt/Ti/Si substrates, PZT films are deposited at 350 $^{\circ}C$ by rf magnetron sputtering. The X-ray diffusion (XRD) was confirmed the formation of PZT thin film. Leakage current characteristics were improved with decreasing the post annealing temperature of PZT thin film. RTA annealed film on the 700$^{\circ}C$ shows ferroelectric and electrical properties with a remanent polarization of 12.4${\mu}$C/$\textrm{cm}^2$ coercive field of 117kV/cm, leakage current J= 6.2${\times}$10$\^$-6/ A/$\textrm{cm}^2$

• Transactions on Electrical and Electronic Materials
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• v.15 no.1
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• pp.16-19
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• 2014

Charge trapping nonvolatile memory capacitors with $ZrO_2$ as charge trapping layer were fabricated, and the effects of post annealing atmosphere ($NH_3$ and $N_2$) on their memory storage characteristics were investigated. It was found that the memory windows were improved, after annealing treatment. The memory capacitor after $NH_3$ annealing treatment exhibited the best electrical characteristics, with a 6.8 V memory window, a lower charge loss ~22.3% up to ten years, even at $150^{\circ}C$, and excellent endurance (1.5% memory window degradation). The results are attributed to deep level bulk charge traps, induced by using $NH_3$ annealing.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.265-270
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• 2017

4H-SiC has attracted attention for high-power and high-temperature metal-oxide-semiconductor field-effect transistors (MOSFETs) for industrial and automotive applications. The gate oxide in the 4H-SiC MOS system is important for switching operations. Above $1000^{\circ}C$, thermal oxidation initiates $SiO_2$ layer formation on SiC; this is one advantage of 4H-SiC compared with other wide band-gap materials. However, if post-deposition annealing is not applied, thermally grown $SiO_2$ on 4H-SiC is limited by high oxide charges due to carbon clusters at the $SiC/SiO_2$ interface and near-interface states in $SiO_2$; this can be resolved via low-temperature deposition. In this study, low-temperature $SiO_2$ deposition on a Si substrate was optimized for $SiO_2/4H-SiC$ MOS capacitor fabrication; oxide formation proceeded without the need for post-deposition annealing. The $SiO_2/4H-SiC$ MOS capacitor samples demonstrated stable capacitance-voltage (C-V) characteristics, low voltage hysteresis, and a high breakdown field. Optimization of the treatment process is expected to further decrease the effective oxide charge density.

• Korean Journal of Materials Research
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• v.24 no.6
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• pp.285-292
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• 2014

Commercial activated-carbon used as the electrode material of an electric double-layer capacitor (EDLC) was posttreated with various acids and alkalis to increase its capacitance. The carbon samples prepared were then heat-treated in order to control the amount of acidic functional groups formed by the acid treatments. Coin-type EDLC cells with two symmetric carbon electrodes were assembled using the prepared carbon materials and an organic electrolyte. The electrochemical performance of the EDLC was measured by galvanostatic charge-discharge, cyclic voltammetry, and electrochemical impedance spectroscopy. Among the various activated carbons, the carbon electrodes (CSsb800) prepared by the treatments of coconutshell-based carbon activated with NaOH and $H_3BO_5$, and then heat treated at $800^{\circ}C$ under a flow of nitrogen gas, showed relatively good electrochemical performance. Although the specific-surface-area of the carbon-electrode material ($1,096m^2/g$) was less than that of pristine activated-carbon ($1,122m^2/g$), the meso-pore volume increased after the combined chemical and heat treatments. The specific capacitance of the EDLC increased from 59.6 to 74.8 F/g (26%) after those post treatments. The equivalent series resistance of EDLC using CSsb800 as electrode was much lower than that of EDLC using pristine activated carbon. Therefore, CSsb800 exhibited superior electrochemical performance at high scan rates due to its low internal resistance.

• Transactions on Electrical and Electronic Materials
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• v.12 no.3
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• pp.127-130
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• 2011

We investigated the effects of $O_2$ annealing (i.e., temperature and time) on the characteristics of hafnium silicate ($HfSi_xO_y$) films deposited on a Si substrate by atomic layer deposition process (ALD). We found that the post deposition annealing under oxidizing ambient causes the oxidation of residual Hf metal components, resulting in the improvement of electrical characteristics (e.g., hysteresis window and leakage current are decreased). In addition, we observed the annealing temperature is more important than the annealing time for post deposition annealing. Based on these observations, we suggest that post deposition annealing under oxidizing ambient is necessary to improve the electrical characteristics of $HfSi_xO_y$ films deposited by ALD. However, the annealing temperature has to be carefully controlled to minimize the regrowth of interfacial oxide, which degrades the value of equivalent oxide thickness.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.136-139
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• 1999

The post-annealing treatments on RF (Radio Frequency) magnetron sputtered PZI(Pb$\_$1.05/(Zr$\_$0.52/, Ti$\_$0.48/)O$_3$thin films(4000${\AA}$) have been investigated. for a structure of PZT/Pt/Ti/SiO$_2$/Si Crystallization pproperties of PZT films were strongly dependent on RTA(Rapid Thermal Annealing) annealing temperature. We were able to obtain a perovskite structure of PZT at a low temperature of 600$^{\circ}C$. P-E curves of Pd/PZT/Pt capacitor annealed at 700$^{\circ}C$ demonstrate typical hysteresis loops. The measured values of P$\_$r/, E$\_$c/, by post annealed at 700$^{\circ}C$ were 12.1 ${\mu}$C/$\textrm{cm}^2$, 120KV/cm respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.33-36
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• 1999

In this paper, $Ba_{0.5}$Sr$_{0.5}$TiO$_3$ thin-films were prepared on Pt/Ti/Si0$_2$/Si substrates by RF magnetron sp-uttering method. We investigated electric and dielectric properties of BST thin-films with various ann-ealing temperature using in-sute RTA. Deposition conditions of BST films were set substrate temperat-ure, 30$0^{\circ}C$ and working gas ratio, Ar:O$_2$=90:10. After BST films deposited, we fabricated a capacitor of MIM structure with Al top electrode for measurement. Post-annealing using RTA performed at 40$0^{\circ}C$, $600^{\circ}C$, 80$0^{\circ}C$ for 60 sec, respectively. Also we exacted crystallization and composition of BST thin-films by XRD analysis. In measurement result, this capacitors showed a dielectric constant of about 200 at 1MHz and leakage current density of 5$\times$10$^{-8}$ A/$\textrm{cm}^2$ at 1.5V Microstructure of BST thin-films exhibited effective quality in low-temperature annealed 71ms than high-temperature annealed 71ms.s.s.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.12
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• pp.1001-1007
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• 2001

In this study, high dielectric materials, (Pb,La)Ti $O_3$ thin films were fabricated by PLD (Pulsed Laser Deposition) method and investigated in terms of structural and electrical characteristics in order to develope the dielectric materials for the use of new capacitor layers of Giga bit-level DRAM. The deposition conditions were examined in order to fabricate uniform thin films through systematic changes of oxygen pressures and substrate temperature. The uniform thickness and smooth morphology of (P $b_{0.72}$L $a_{0.28}$)Ti $O_3$ thin films were obtained at the conditions of substrate-target distance 5.5[cm], laser energy density 2.1[J/$\textrm{cm}^2$], oxygen pressure 200[mTorr] and substrate temperature 500[$^{\circ}C$]. After the (P $b_{0.72}$L $a_{0.28}$)Ti $O_3$ thin films were fabricated under the above conditions, they were post-annealed by RTA process in order to increase the dielectric constant. The film thickness of 1200 [$\AA$] had dielectric constant 821. Assuming that operating voltage is 2V, leakage current density of (P $b_{0.72}$L $a_{0.28}$)Ti $O_3$ thin films would result into 10$^{-7}$ [A/$\textrm{cm}^2$] and satisfied the specification of 256M DRAM planar capacitor, 4$\times$10$^{-7}$ [A/$\textrm{cm}^2$]m}^2$]