• The Transactions of the Korea Information Processing Society
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• v.5 no.10
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• pp.2575-2583
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• 1998

The productionof the highly relible softwae systems and theirs performance evaluation hae become important interests in the software industry. The software evaluation has been mainly carried out in ternns of both reliability and performance of software system. Software reliability is the probability that no software error occurs for a fixed time interval during software testing phase. These theoretical software reliability models are sometimes unsuitable for the practical testing phase in which a software error at a certain testing stage occurs by causes of the imperfect debugging, abnornal software correction, and so on. Such a certatin software testing stage needs to be considered as an outlying stage. And we can assume that the software reliability does not improve by means of muisance factor in this outlying testing stage. In this paper, we discuss Bavesian software reliability growth modeling and estimation procedure in the presence of an imidentitied outlying software testing stage by the modification of Jehnski Moranda. Also we derive the Bayes estimaters of the software reliability panmeters by the assumption of prior information under the squared error los function. In addition, we evaluate the proposed software reliability growth model with an unidentified outlying stage in an exchangeable model according to the values of nuisance paramether using the accuracy, bias, trend, noise metries as the quantilative evaluation criteria through the compater simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.21-31
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• 2010

This paper presents a design of PLL and SSCG for reducing the EMI effect at the electronic machinery and tools for DisplayPort application. This system is composed of the essential element of PLL and Charge-Pump2 and Reference Clock Divider to implement the SSCG operation. In this paper, 270MHz/162MHz dual-mode PLL that can provide 10-phase and 1.35GHz/810MHz PLL that can reduce the jitter are designed for 2.7Gbps/162Gbps DisplayPort application. The jitter can be reduced drastically by combining 270MHz/162MHz PLL with 2-stage 5 to 1 serializer and 1.35GHz PLL with 2 to 1 serializer. This paper propose the frequency divider topology which can share the divider between modes and guarantee the 50% duty ratio. And, the output current mismatch can be reduced by using the proposed charge-pump topology. It is implemented using 0.13 um CMOS process and die areas of 270MHz/162MHz PLL and 1.35GHz/810MHz PLL are $650um\;{\times}\;500um$ and $600um\;{\times}\;500um$, respectively. The VCO tuning range of 270 MHz/162 MHz PLL is 330 MHz and the phase noise is -114 dBc/Hz at 1 MHz offset. The measured SSCG down spread amplitude is 0.5% and modulation frequency is 31kHz. The total power consumption is 48mW.

• Geophysics and Geophysical Exploration
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• v.13 no.1
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• pp.51-60
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• 2010

To determine subglacial topography and internal features of the Fourcade Glacier on King George Island in Antarctica, helicopter-borne and ground-towed ground-penetrating radar (GPR) data were recorded along four profiles in November 2006. Signature deconvolution, f-k migration velocity analysis, and finite-difference depth migration applied to the mixed-phase, single-channel, ground-towed data, were effective in increasing vertical resolution, obtaining the velocity function, and yielding clear depth images, respectively. For the helicopter-borne GPR, migration velocities were obtained as root-mean-squared velocities in a two-layer model of air and ice. The radar sections show rugged subglacial topography, englacial sliding surfaces, and localised scattering noise. The maximum depth to the basement is over 79m in the subglacial valley adjacent to the south-eastern slope of the divide ridge between Fourcade and Moczydlowski Glaciers. In the ground-towed profile, we interpret a complicated conduit above possible basal water and other isolated cavities, which are a few metres wide. Near the terminus, the GPR profiles image sliding surfaces, fractures, and faults that will contribute to the tidewater calving mechanism forming icebergs in Potter Cove.

• Explosives and Blasting
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• v.30 no.2
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• pp.86-97
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• 2012

Ground vibration induced by a bench blasting in the construction site should cause the damage to the structure and indirect damage to a human body, and the vibration level is most practical descriptor for regulating the damage to human body and peak particle velocity is the descriptor for direct damage assesment of the structure. Meantime, the vibration level has not been considered for the blasting design but this study is the case that apply not only peak particle velocity but also vibration level on the blasting design. Also, we strongly believe that this study will be helpful for the management in the blasting site which some civil appeal is concerned. Total 232 measurements of both ppv and vibration level was used to estimate the scale distance. When the regulating threshold was ppv 0.3 cm/s and vibration level 75 decibel, the charge per delay to be estimated with vibration level could be recommended by 1.2~1.4 times than it of ppv. So, it is proven that considering vibration level on the blasting design is reasonable for not only prevention of the civil appeals but also effective blasting. Again, the blasting design which follows the law, "Noise and Vibration Control Act" can actually serve good condition to carry much more economical and effective blasting. The instruments used for this study are the SV-1 model, as first instrument in korea which can measure vibration velocity and vibration level at the same time.

• Korean Journal of Optics and Photonics
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• v.26 no.3
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• pp.155-161
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• 2015

We report the design and performance analysis of an off-axis three-mirror telescope as the fore optics for a new hyperspectral sensor aboard a small unmanned aerial vehicle (UAV), for low-altitude coastal remote sensing. The sensor needs to have at least 4 cm of spatial resolution at an operating altitude of 500 m, $4^{\circ}$ field of view (FOV), and a signal to noise ratio (SNR) of 100 at 660 nm. For these performance requirements, the sensor's optical design has an entrance pupil diameter of 70 mm and an F-ratio of 5.0. The fore optics is a three-mirror system, including aspheric primary and secondary mirrors. The optical performance is expected to reach $1/15{\lambda}$ in RMS wavefront error and 0.75 in MTF value at 660 nm. Considering the manufacturing and assembling phase, we determined the alignment compensation due to the tertiary mirror from the sensitivity, and derived the tilt-tolerance range to be 0.17 mrad. The off-axis three-mirror telescope, which has better performance than the fore optics of other hyperspectral sensors and is fitted for a small UAV, will contribute to ocean remote-sensing research.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.8 s.338
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• pp.33-40
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• 2005

This paper presents a structure of the searcher using a diversity in array antenna systems operating in the cdma2000 1x signal environments. The new technique exploits the fact that the In-phase and quadrature components of interferers can respectively be viewed as an independent gaussian noise at each antnna element in most practical cdma signal environments. The proposed PN acquisition scheme is a singles-dwell PN acquisition system consisting of two stages, that is, the searching stage and the verification stage. The searching stage independently correlates the receiver multiple signals with PN generator of each antenna element for obtaining the synchronous energy at the entire region. Then, the searching results of each antenna element are non-coherently combinind. The verification stage compares the searching energy with the optimal threshold, which is predesigned in the lock detector, and decides whether the acquisition is successful or fail. In this paper, we analyzed the effect of tile diversity order to determine the mean acquisition time. In general, it is known that the mean acquisition time significantly decrease as the number of antenna elements increases. But, as the diversity order goes up, the enhancement of the performance is saturated. Therefore, to decrease the mean acquisition time of the searcher, we must design the optimal array antenna systems by considering the operating SNR range of the receiver, the probability of detection $P_D$ and that of false alarm $P_{FA}$ . The Performance of the proposed PN acquisition scheme is analyzed in frequency selective Rayleigh fading channels. In this paper, the effect of the number of antenna elements on PN acquisition scheme is shown according to the probability of detection $P_D$ and that of false alarm $P_{FA}$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.117-124
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• 2009

This paper describes a 3 to 5 GHz frequency synthesizer for MB-OFDM (Multi-Band OFDM) UWB (Ultra- Wideband) application using 0.13 ${\mu}m$ CMOS process. The frequency synthesizer operates in the band group 1 whose center frequencies are 3432 MHz 3960 MHz, and 4488 MHz. To cover the overall frequencies of group 1, an efficient frequency planning minimizing a number of blocks and the power consumption are proposed. And, a high-frequency VCO and LO Mixer architecture are also presented in this paper. A new mixed coarse tuning scheme that utilizes the MIM capacitance, the varactor arrays, and the DAC is proposed to expand the VCO tuning range. The frequency synthesizer can also provide the clock for the ADC in baseband modem. So, the PLL for the ADC in the baseband modem can be removed with this frequency synthesizer. The single PLL and two SSB-mixers consume 60 mW from a 1.2 sV supply. The VCO tuning range is 1.2 GHz. The simulated phase noise of the VCO is -112 dBc/Hz at 1 MHz offset. The die area is 2 ${\times}$ 2mm$^2$.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.2
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• pp.159-165
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• 2012

This paper deals with the performance comparison of adaptive equalization algorithm, MMA and SCA, that is used for the minimization of the distortion and noise effect in the communication channel.. The transmitting signal will be distorted and received due to the nonlinearties of magnitude and phase transfer characteristics of communication channel, the compensation of it by using the self adaptive equalizer. The constant modulus has important metric in the self adaptive equalizer, the MMA uses the 2nd and 4th high order statistics of transmitting signal, the SCA uses the 2nd order statistics of transmitting signal only in order to the calculation of it. We compared to the compensation performance of the MMA and SCA by the computer simulation that are possible to the compensation of the two kinds of transfer characteristics at same times by the relatively simple arithmatic operation. We used to the recovered constellation, residual isi and MSE, SER that are the essential index for the comparison of the adaptive equalizer. The result of performance comparison of algorithms, the MMA which uses the high order statistics of transmitting signal has good performance in the MSE and SER compared to the SCA which is using the low order statistics. But in the recovered costellation and residual isi, the SCA has a good than the MMA.