• Journal of the Korean Institute of Telematics and Electronics
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• v.12 no.3
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• pp.20-25
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• 1975

A microwave oscillator stabilized by a phase-locked loop (PLL) is developed. The PLL system is chosen 'compared with the cavity stabilized oscillator in view of the domestic manufacturing, because special machining and materials are needed for the latter. A sampler with a low pass filter is shown to be used as a phase detector in the PLL, and the sampler capable of sampling up to 4GHz is developed for this use. Frequency stability of about 10-6 is obtained from the developed microwave oscillator, operating at 2.16 GHz with more than 120 milliwatts output power, Ivhereby a crystal oscillator operating at about 110MHz is used as a reference source in the PLL. The capturing range of this oscillator is extended up to its lock-in-range of about 10MHz by employing a search oscillator in the system.

• The KIPS Transactions:PartA
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• v.10A no.3
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• pp.247-254
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• 2003

This paper describes a Delay Locked Loop (DLL) with low supply voltage and wide lock range for Synchronous DRAM which employs Double Data Rate (DDR) technique for faster data transmission. To obtain high resolution and fast lock-on time, a new type of phase detector is designed. The new counter and lock indicator structure are suggested based on the Dual-clock dual-data Flip Flop (DCDD FF). The DCDD FF reduces the size of counter and lock indicator by about 70%. The delay line is composed of coarse and fine units. By the use of fast phase detector, the coarse delay line can detect minute phase difference of 0.2 nsec and below. Aided further by the new type of 3-step vernier fine delay line, this DLL circuit achieves unprecedented timing resolution of 25psec. This DLL spans wide locking range from 500MHz to 500MHz and generates high-speed clocks with fast lock-on time of less than 5 clocks. When designed using 0.25 um CMOS technology with 1.8V supply voltage, the circuit consumes 32mA at 500MHz locked condition. This circuit can be also used for other applications as well, such as synchronization of high frequency communication systems.

• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.131-136
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• 2008

System을 통해 출력되는 신호를 측정할 때 정확한 측정을 방해하는 요소로 잡음이 있다. 이런 신호 측정의 방해 요소인 잡음을 제거 하는 방법 중의 하나로 Lock-in Amp(LIA)가 사용되고 있다. 본 논문에서는 잡음 신호의 제거를 위해 사용 하는 LIA를 제작 하고 특성을 파악 하였으며 RF통신을 이용하여 무선 형태로 제작 하였다. 현재 상용화된 LIA는 프로브를 통한 유선으로 측정신호의 입력을 받게 되지만 본 논문에서 제작된 LIA는 무선신호 형태로 입력 하게 된다. RF통신의 케리어 주파수는 447.9[MHz]로 Digital GMSK 변복조방식을 이용하였다. LIA의 제작은 Dual Phase Sensitive Detecter을 사용하였으며, 주요 구성 요소인 Phase Locked Loop, Phase Shifter, Phase Sensitive Detector, Low Pass Filter등의 구조와 특성을 조사하였다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.10
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• pp.1147-1158
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• 2008

In this paper, we designed a phase-looking circuit that locks the 16.8 GHz VTDRO to a 700 MHz SAW oscillator using SPD as a phase detector Direct phase locking with loop filter alone causes the problem of lock time, so VTDRO is phase leered by loop filter with the aid of time varying square wave current generator. The current generator is related to the loop filter and needs the systematic toning. In this paper, a systematic design of the current generator and loop filter is presented. The fabricated PLDRO shows a stabilized frequency of 16.8 GHz, a output power 6.3 dBm, and a phase noise of -101 dBc/Hz at the 100 kHz offset.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.9
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• pp.1692-1701
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• 1994

Macromodeling technology is useful to simulate and analyze the performance of new elements and complicated circuits or systems without any changes in today's general simulator, PSPICE. In this paper, Phase Locked Loop(PLL) is designed using macromodeling technique. The PLL macromodel has two basic sub-macromodels of the phase detector and the voltage controlled oscillator(VCO). The PLL macromodel has two open terminals for inserting RC low pass filter. The PLL macromodel is simulated using simulation parameters of LM565CN manufactured in the National company. At a free-running frequency, 2500Hz, upper lock range and lower capture range was 437Hz, 563Hz, respectively. Also, experimental results and simulation results of LM565CN PLL show good agreement.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.8
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• pp.1558-1563
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• 2007

In this paper, phase-locked loop (PLL) of a combinational architecture consisting of an adaptive bandwidth and fractional-N is presented to improve performances and reduce the order of ${\Delta}{\Sigma}$ modulator while maintaining equivalent or better performance with fast locking. The architecture of adaptive bandwidth PLL was simulated by HSPICE using 0.35m CMOS parameters. The behavioral simulation of the proposed adaptive bandwidth fractional-N PLL with a ${\Delta}{\Sigma}$ modulator was carried out by using MatLab to determine if the architecture could achieve the objectives. The HSPICE simulation showed that this type of PLL was able to fast locking, and reduce fractional spurs about 20dB.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.11 no.4
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• pp.70-79
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• 2012

A design guide to type-3 PLLs for FMCW radars is provided. To do that, the cross-over frequencies of the open-loop transfer functions were normalized to 1 Hz and closed-loop properties were compared through simulations using Pspice. As a result, several guides to design type-3 PLLs were provided: 1) secure 45 degrees of phase margin, 2) locate two zeroes at an identical frequency, and 3) poles may be added to raise order of the PLL at higher frequencies than the cross-over frequency of the open-loop transfer function about ten times.

• Korean Journal of Optics and Photonics
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• v.11 no.5
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• pp.330-334
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• 2000

A new pha~e lock loop (PLL) IS proposed and demonstrated fat clock recovery from 40 Gblt/s time-dIvision-multiplexed (TDM) optical pulse tri.lin, The proposed clock lecovery scheme lmproves the Jitter effecl cOlmng from the clock. pulse laser of harmonically-mode locked flber laser The cross-corrdation frequency component between the optical Signa] and an optical clock pulse tram is deteCled as a fonr-wave-mixing (FWM) SIgnal generated in SOA. The lock-in freqnency range of the clod. recovery IS found to be within 10 KHz. 0 KHz.

• Journal of the Korean Institute of Telematics and Electronics
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• v.19 no.5
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• pp.55-67
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• 1982

In this Paper new results relating to the acquisition behavior of a class of first-and secondorder digital phase-locked loops (DPLL) originally proposed by Reddy and Cupta are presented in the absence of noise. It has been found that the number of quantization levels L and the number of phase error states N play important roles in acquisition. For a given L-level quantizer, as N increases, the acquisition time increases, and the lock range decreases. However, the deviation of the steady state phase error decreases in this case. When L increases, the acquisition time decreases, and the lock range increases. However, variation of L affects little for the steady state phase error. In addition, the effects of a loop filter on acquisition have also been considered. One can get smaller acquisition time and larger lock range as the filter parameter value becomes larger. However, deviation of the steady state phase error increases in that case. Analytical results have been verified by computer simulation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07b
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• pp.1132-1135
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• 2002

In this paper, we propose a phase-locked loop (PLL) with dual loops in which advantages of both loops can be combined. Frequency-locked loop (FLL) which is composed of two frequency-to-voltage converters (FVC) and an amplifier makes the frequency synchronize very fast and output signal is synchronized in phase with the input reference signal by charge pump PLL. This structure can improve the trade-off between acquisition behavior and locked behavior.