• The Journal of Churna Manual Medicine for Spine and Nerves
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• v.8 no.1
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• pp.15-26
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• 2013

Objectives: The purpose of this study is to find out the relationship between lumbar lordotic angle and low back pain patterns. Methods: We randomly selected the 1191 patients (595 males, 596 females) who have visited Bu-Chun Jaseng Hospital of Korean Medicine with low back pain. We have taken lumbar x-ray films and measured their lumbar lordotic angle, the angle formed between L1 superior margin and S1 superior margin. We investigated 1191 patients' low back pain patterns(date of occurence, existence of radiating pain, trend of increasing pain with lumbar extention and flexion, trend of increasing pain with standing and sitting positions) and analysed the relationship between lumbar lordotic angle and low back pain patterns. Results: 1. The lumbar lordotic angle of the acute phase patient is more straight than the chronic one. 2. The lumbar lordotic angle of the patients with radiating pain is more straight than the patients without radiating pain. 3. At acute phase, the lumbar lordotic angle of the patients with increasing pain from lumbar extention is more straight than those with increasing pain from lumbar flexion. 4. At chronic phase, the lumbar lordotic angle of the patients with increasing pain from lumbar flexion is more straight than those with increasing pain from lumbar extention. Conclusions: There was a significant correlation between lumbar lordotic angle and low back pain.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.2
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• pp.167-174
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• 2015

This study describes how digital time delay deteriorates control performance in zero voltage switching (ZVS) phase-shifted full bridge (PSFB) converter. The small-signal model of the ZVS PSFB converter is derived from the buck-converter small-signal model. Digital time delay effects have been considered according to the digital sampling methods. The analysis verifies that digital time delays reduce the stability margin of the converter, and the double sampling technique exhibits better performance than the single sampling technique. Both simulation and experimental results based on 250 W ZVS PSFB confirm the validity of the analyses performed in the study.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.11
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• pp.901-907
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• 2000

As the minimum feature size for making ULSI approaches the wavelength of light source in optical lithography, the aerial image is so hardly distorted because of the optical proximity effect that the accurate mask image reconstruction on wafer surface is almost impossible. We applied the Optical Proximity Correction(OPC) on isolated patterns assuming Attenuated Phase Shift Mask(APSM) as well as binary mask, to correct the widening of isolated patterns. In this study, we found that applying OPC to APSM shows much better improvement not only in enhancing the resolution and fidelity of t도 images but also in enhancing the process margin than applying OPC to the binary mask. Also, we propose the OPC method of APSM for isolated patterns, the size of which is less than the wavelength of the ArF excimer laser. Finally, we predicted the resolution limit of optical lithography through the aerial image simulation.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.11 no.4
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• pp.70-79
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• 2012

A design guide to type-3 PLLs for FMCW radars is provided. To do that, the cross-over frequencies of the open-loop transfer functions were normalized to 1 Hz and closed-loop properties were compared through simulations using Pspice. As a result, several guides to design type-3 PLLs were provided: 1) secure 45 degrees of phase margin, 2) locate two zeroes at an identical frequency, and 3) poles may be added to raise order of the PLL at higher frequencies than the cross-over frequency of the open-loop transfer function about ten times.

• Journal of Power Electronics
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• v.12 no.4
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• pp.623-631
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• 2012

In this paper, a digital controller design procedure is presented for single-phase voltage-doubler boost rectifiers (VDBR). The model derivation of the single-phase VDBR is performed in the s-domain. After that the simplified equivalent z-domain models are derived. These z-domain models are utilized to design the input current and the output dc-link voltage controllers. For the controller design in the z-domain, the traditional K-factor method is modified by considering the nature of the digital controller. The frequency pre-warping and anti-windup techniques are adapted for the controller design. By using the proposed method, the phase margin and the control bandwidth are accurately achieved as required by controller designers in a practical frequency range. The proposed method is applied to a 2.5 kVA single-phase VDBR for Uninterruptible Power Supply (UPS) applications. From the simulation and the experimental results, the effectiveness of the proposed design method has been verified.

• Journal of Power Electronics
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• v.18 no.3
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• pp.944-953
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• 2018

This paper proposes an analysis method based on the magnitude-phase dynamic theory for isolated power systems with static synchronous compensators (STATCOMs). The stability margin of an isolated power system is greatly reduced when a load is connected, due to the disadvantageous features of the self-excited induction generators (SEIGs). To analyze the control process for system stability and to grasp the dynamic characteristics in different timescales, the relationships between the active/reactive components and the phase/magnitude of the STATCOM output voltage are derived in the natural reference frame based on the magnitude/phase dynamic theory. Then STATCOM equivalent mechanical models in both the voltage time scale and the current time scale are built. The proportional coefficients and the integral coefficients of the control process are converted into damping coefficients, inertia coefficients and stiffness coefficients so that analyzing its controls, dynamic response characteristics as well as impacts on the system operations are easier. The effectiveness of the proposed analysis method is verified by simulation and experimental results.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.2
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• pp.76-80
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• 2014

Dual-gate PCRAM which unify capacitor-less DRAM and NVM using a PCM instead of a typical SONOS flash memory is proposed as 1 transistor. $VO_2$ changes its phase between insulator and metal states by temperature and field. The front-gate and back-gate control NVM and DRAM, respectively. The feasibility of URAM is investigated through simulation using c-interpreter and finite element analysis. Threshold voltage of NVM is 0.5 V that is based on measured results from previous fabricated 1TPCM with $VO_2$. Current sensing margin of DRAM is 3 ${\mu}A$. PCM does not interfere with DRAM in the memory characteristics unlike SONOS NVM. This novel unified dual-gate PCRAM reported in this work has 1 transistor, a low RESET/SET voltage, a fast write/erase time and a small cell so that it could be suitable for future production of URAM.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1426-1427
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• 2006

Chalcogenide based phase-change memory has a high capability and potential for the next generation nonvolatile memory device. Fast writing speed, low writing voltage, high sensing margin, low power consume and long cycle of read/write repeatability are also good advantages of nonvolatile phase-change memory. We have been investigated the new material for the phase-change memory. Its composition is consists of chalcogenide $Ge_{1}Se_{1}Te_2$ material. We made this new material to solve problems of conventional phase-change memory which has disadvantage of high power consume and high writing voltage. In the present work, we are manufactured $Ge_{1}Se_{1}Te_{2}/Ge_{2}Sb_{2}Te_{5}/Ge_{1}Se_{1}Te_{2}$ and $Ge_{2}Sb_{2}Te_{5}/Ge_{1}Se_{1}Te_{2}/Ge_{2}Sb_{2}Te_{5}$ sandwich triple layer structure devices are manufactured to investigate its electrical properties. Through the present work, we are willing to ensure a potential of substitutional method to overcome a crystallization problem on PRAM device.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.468-471
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• 1997

In this paper, we investigate the time-sampling effects on the digital implementation of singular perturbation based STT autopilot with excellent performance and propose a compensation method for the time-sampling effects. In digitization of analog STT autopilot, it is found that the stability margin of the fast dynamics is mostly affected to lead to rapid decrease. Under the this analysis, a composite digital controller with additional compensator for fast dynamics is proposed to improve the time-sampling effect and a simulation verifies the result.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.133-136
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• 2000

A new Op-Amp output buffer is presented for driving large-size LCD panels. The proposed Op-Amp is designed by combining a common source and a common drain amplifier to have a high slew rate and to minimize the quiescent current. The proposed circuits are simulated in a high-voltage 0.6${\mu}{\textrm}{m}$ CMOS process, dissipates only 20${\mu}{\textrm}{m}$ static current, and have 83dB open-loop DC gain and 60$^{\circ}$phase margin.