• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.12
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• pp.773-776
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• 1999

A newly proposed lateral dual-gate thyristor was fabricated and measured, which has excellent current saturation characteristics of $1200A/cm^2$ even at an anode-gate voltage of 29V, through the elimination of the structurally existing parasitic thyristor. And through the comparison with the LIGBT, the excellent current saturation characteristics of a newly proposed device was verified.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.392-395
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• 2003

For the first time, the new dual trench gate Emitter Switched Thyristor is proposed for eliminating snap-back effect which leads to a lot of serious problems of device applications. Also, the parasitic thyristor that is inherent in the conventional EST is completely eliminated in the proposed EST structure, allowing higher maximum controllable current densities for ESTs. Moreover, the new dual trench gate allows homogenous current distribution throughout device and preserves the unique feature of the gate controlled current saturation of the thyristor current. The conventional EST exhibits snap-back with the anode voltage and current density 2.73V and $354/{\S}^2$, respectively. But the proposed EST exhibits snap-back with the anode voltage and current density 0.93V and $58A/{\S}^2$, respectively. Saturation current density of the proposed EST at anode voltage 6.11V is $3797A/{\S}^2$. The characteristics of 700V forward blocking of the proposed EST obtained from two dimensional numerical simulations (MEDICI) is described and compared with that of the conventional EST.

• Transactions on Electrical and Electronic Materials
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• v.4 no.2
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• pp.15-19
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• 2003

In this paper, the new dual trench gate Emitter Switched Thyristor (DTG-EST) is proposed for improving snap-back effect which leads to a lot of serious problems of device applications. Also the parasitic thyristor that is inherent in the conventional EST is completely eliminated in this structure, allowing higher maximum controllable current densities for ESTs. The conventional EST exhibits snap-back with the anode voltage and current density 2.73V and 35A/$\textrm{cm}^2$, respectively. But the proposed DTG-EST exhibits snap-back with the anode voltage and current density 0.96V and 100A/$\textrm{cm}^2$, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05b
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• pp.27-30
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• 2003

In this paper, the new dual trench gate Emitter Switched Thyristor (DTG-EST) is proposed for improving snap-back effect which leads to a lot of serious problems of device applications. And the parasitic thyristor that is inherent in the conventional EST is completely eliminated in this structure, allowing higher maximum controllable current densities for ESTs. The conventional EST exhibits snap-back with the anode voltage and current density 2.73V and $35A/cm^2$, respectively. But the proposed DTG-EST exhibits snap-back with the anode voltage and current density 0.96V and $100A/cm^2$, respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.3
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• pp.183-189
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• 2010

In this paper, the trench gate emitter switched thyristor(EST) withl trench gate electrode is proposed for improving snap-back effect which leads to a lot of problems in device applications. The parasitic thyristor which is inherent in the conventional EST is completely eliminated in this structure, allowing higher maximum controllable current densities for ESTs. The dual trench gate allows homogenous current distribution in the EST and preserves the unique feature of the gate controlled current saturation of the thyristor current. The characteristics of the 1700 V forward blocking EST obtained from two-dimensional numerical simulations (MEDICI) is described and compared with that of a conventional EST. we carried out layout, design and process of EST devices.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.172-180
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• 2003

Based on simulation results and accompanying analysis, we suggest a thyristor-type ESD protection device structure suitable for implementation in standard CMOS processes to reduce the parasitic capacitances added to the input nodes, which is very important in CMOS RF ICs. We compare DC breakdown characteristics of the suggested device to those of a conventional NMOS protection device to show the benefits of using the suggested device for ESD protection. The characteristic improvements are demonstrated and the corresponding mechanisms are explained based on simulations. Structure dependencies are also examined to define the optimal structure. AC simulation results are introduced to estimate the magnitude of reduction in the added parasitic capacitance when using the suggested device for ESD protection. The analysis shows a possibility of reducing the added parasitic capacitance down to about 1/40 of that resulting with a conventional NMOS protection transistor, while maintaining robustness against ESD.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.7
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• pp.32-37
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• 1993

A novel insulated gate bipolar transister (IGBT), called insulated trench cathode IGBT (ISTC-IGBT), is proposed. ISTC-IGBT has a trenched well with the shallow P$^{+}$ juction in the conventional IGBT structure. The proposed structure has the capability of effectively suppressing the parasitic thyristor latchup. The holding current of ISTC-IGBT is about 2.2 times greater than that of the conventional IGBT. Detailed analysis of the latchup characteristics of ISTC-IGBT is performed by using the two-dimensional device simulator, PISCES-II B.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.4
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• pp.490-494
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• 2014

In this paper, a design of high-speed power-off circuit and analysis. The incidence of high-dose transient radiation into the silicon-based semiconductor element induces the photocurrent due to the creation of electron-hole pairs, which causes the upset phenomenon of active elements or triggers the parasitic thyristor in the element, resulting in latch-up. High speed power-off circuit was designed to prevent burn-out of electronic device caused by Latch-up. The proposed high speed power-off circuit was configured with the darlington transistor and photocoupler so that the power was interrupted and recovered without the need for an additional circuit, in order to improve the existing problem of SCR off when using the thyristor. The discharge speed of the high speed power interruption circuit was measured to be 19 ${\mu}s$ with 10 ${\mu}F$ and 500 ${\Omega}$ load, which was 98% shorter than before (12.8 ms).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.9
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• pp.551-554
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• 2014

This paper was showed latch up characteristics of super junction power MOSFET by parasitic thyristor according to trench etch angle. As a result of research, if trench etch angle of super junction MOSFET is larger, we obtained large latch up voltage. When trench etch angle was $90^{\circ}$, latch up voltage was more 50 V. and we got 700 V breakdown voltage. But we analyzed on resistance. if trench etch angle of super junction MOSFET is larger, we obtained high on resistance. Therefore, we need optimal point by simulation and experiment for solution of trade off.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.3
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• pp.422-426
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• 2012

Transient radiation is emitted during a nuclear explosion. Transient radiation causes a fatal error in the CMOS circuit as a Upset and Latch-up. In this paper, transient radiation NMOS, PMOS, INVERTER SPICE model was proposed on the basisi of transient radiation effects analysis using TCAD(Technology Computer Aided Design). Photocurrent generated from the MOSFET internal PN junction was expressed to the current source and Latch-up phenomenon in the INVERTER was expressed to parasitic thyristor for the transient radiation SPICE model. For example, the proposed transient radiation SPICE model was applied to CMOS NAND circuit. SPICE simulated characteristics were similar to the TCAD simulation results. Simulation time was reduced to 120 times compared to TCAD simulation.