• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.899-902
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• 2003

Chip Pin Parasitic은 실제 Chip Pad에서부터 Bonding Wire를 통한 Package Lead Frame까지를 의미한다. 여기서, Lead Frame 및 Bonding Wire에서 Inductance 및 작은 저항이 보이고, Chip Pad에서의 Capacitance, 그리고 Pad 부터 Ground까지의 Return Path에서 발생하는 저항이 보인다. 이들을 모두 합하면 L, R, C의 Series로 나타낼 수 있다. 본 논문에서는 이런 Chip Pin Parasitic을 추출 하기 위해서 TDR(Time Domain Reflectometer)과 NA(Network Analyzer)를 사용하였는데, TDR의 경우 PCB를 제작하여 Chip을 Board위에 붙인 후 Time Domain에서 측정 하였고 NA의 경우 Pico Probe를 이용하여 Chip pin에 직접 Probing해서 Smith Chart를 통하여 Extraction 값을 추출했다. 이 경우, NA를 이용한 측정이 좀 더 정확한 Parasitic 값을 추출할 수 있으리라 예상되겠지만, 실제로 Chip이 구동하기 위해서는 Board위에 있을 때의 상황도 고려해야 하기 때문에 TDR 추출 값과 NA 추출 값을 모두 비교하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.130-133
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• 2011

A comparative study of two capacitance methods to measure the effective channel length in deep-submicron MOSFETs has been made in detail. Since the reduction of the overlap capacitance in the accumulation region is smaller than the addition of the inner fringe capacitance at zero gate voltage, the capacitance method removing the parasitic capacitance in the accumulation region extracts a more accurate effective channel length than the method removing that at zero gate voltage.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.671-674
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• 2005

The series parasitic resistances ($R_s$, $R_g$, $R_d$, $R_{sub}$) of BSIM3v3 RF MOSFET macro model were directly extracted from measured S-parameters in the GHz region by using simple 2-port parameter equations. Also, overlap capacitance and junction capacitance parameters were extracted by tuning $S_{11}$, $S_{12}$, and $S_{22}$ respectively while DC-parameters and all parasitic resistances are fixed at previously extracted values. These data are verified to be accurate by observing good correspondence between modeled and measured S-parameters up to 10GHz.

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.105-106
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• 2016

In low-power grid-connected photovoltaic(PV) system, Single-phase transformerless full-bridge inverter is commonly used. However in transformerless photovoltaic application, the ground parasitic capacitance created by grounding between PV panels and ground. This ground parasitic capacitance inject additional current into the inverter, these currents cause electromagnetic interference problem, safety problem and harmonics problem in PV applications. In order to eliminate the ground current, This paper propose various inverter topologies in PV applications. These proposed inverter topologies are verified through simulation using PSIM.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.270-277
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• 2012

This paper presents a new DAC design strategy to achieve a wideband dynamic linearity by increasing the bandwidth of the output impedance. In order to reduce the dominant parasitic capacitance of the conventional matrix structure, all the cells associated with a unit current source and its control are stacked in a single column very closely (stacked unit cell structure). To further reduce the parasitic capacitance, the size of the unit current source is considerably reduced at the sacrifice of matching yield. The degraded matching of the current sources is compensated for by a self-calibration. A prototype 6-bit 3.3-GS/s current-steering full binary DAC was fabricated in a 1P9M 90 nm CMOS process. The DAC shows an SFDR of 36.4 dB at 3.3 GS/s Nyquist input signal. The active area of the DAC occupies only $0.0546mm^2$ (0.21 mm ${\times}$ 0.26 mm).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.12
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• pp.977-982
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• 2000

Conventional transistors which have vertical structure show increased parasitic capacitance characteristics in accordance with the increase of non-active base area and collector area. These consequently have disadvantage for high speed switching performance. In this paper, a lateral structure transistor which has minimized parasitic capacitance by using SDB(Silicon Direct Bonding) wafer and oxide sidewall isolation utilizing silicon trench technology is presented. Its structural characteristics are designed by ATHENA(SUPREM4), the process simulator from SILVACO International, and its performance is proven by ATLAS, the device simulator from SILVACO International. The performance of the proposed lateral structure transistor is certified through the V$\_$CE/-I$\_$C/ characteristics curve, h$\_$FE/-I$\_$C/ characteristics, and GP-plot. Cutoff Frequency is 13.7㎓.

• Journal of Information Display
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• v.1 no.1
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• pp.29-31
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• 2000

A 21.6" a-Si:H TFT array for direct conversion X-ray detector with 2480 by 3072 pixels is successfully developed. To obtain X-ray image of satisfactory quality, a novel structure with a storage electrode on BCB is proposed. The structure reduces the parasitic capacitance of data line, which is one of the main sources of signal noise. Also, the structure shows greater resistance to failure than that of the conventional design.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.1
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• pp.33-41
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• 2003

In this work, process optimization techniques for high frequency performance of HBTs are presented. The techniques are focused on reducing parasitic base resistance and base-collector capacitance, which are key elements determining the high frequency characteristics of HBTs. Several fabrication techniques, which can significantly reduce the parasitic elements of the HBTs for improved high frequency performance, are proposed and verified by the measured data of the fabricated devices.

• Journal of electromagnetic engineering and science
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• v.14 no.4
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• pp.376-381
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• 2014

We present a CMOS rail-to-rail class-AB amplifier using dynamic current biasing to improve the delay response of the error amplifier in a low-dropout (LDO) regulator, which is a building block for a wireless power transfer receiver. The response time of conventional error amplifiers deteriorates by slewing due to parasitic capacitance generated at the pass transistor of the LDO regulator. To enhance slewing, an error amplifier with dynamic current biasing was devised. The LDO regulator with the proposed error amplifier was fabricated in a $0.35-{\mu}m$ high-voltage BCDMOS process. We obtained an output voltage of 4 V with a range of input voltages between 4.7 V and 7 V and an output current of up to 212 mA. The settling time during line transient was measured as $9{\mu}s$ for an input variation of 4.7-6 V. In addition, an output capacitor of 100 pF was realized on chip integration.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.4A
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• pp.466-471
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• 2004

This paper proposes an advanced circuit for fingerprint sensor signal processing. We increased the voltage between ridge and valley by modifying the parasitic capacitance eliminating circuit of sensor plate. The analog comparator was designed for comparing the sensor signal voltage with the reference signal voltage. 1-Pixel Fingerprint sensor circuit was designed and simulated, and the layout was performed.