• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.396-399
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• 2003

4H-SiC un diodes with field limiting rings(FLRs) were fabricated and characterized. The dependences of reverse breakdown voltage on the number of FLRs, the distance between p-base main junction and first FLR, and activation temperatures, were investigated. Al and B ions were implanted and activated at high temperature to form p-base region and p+ region in the n-epilayer. We have obtained up to 1782V of reverse breakdown voltage in the un diode with two FLRs on loom thick epilayer. The differential on-resistances of the fabricated diode are $5.3m{\Omega}cm^2$ at $100A/cm^2$ and $2.7m{\Omega}cm^2$ at $1kA/cm^2$, respectively. All pn diodes with FLRs have higher avalanche breakdown voltages than that of diode without an FLR. Regardless of the activation temperature, the un diode with a FLR located 5um apart from main junction has the highest mean breakdown voltage around 1600V among the diodes with one ring. On the other hand, the pn diode with two rings showed different behavior with activation temperature. It reveals that high voltage SiC pn diodes with low on-resistance can be fabricated by using the FLR edge termination.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.12
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• pp.100-105
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• 1994

Analytical expressions for the breakdown voltage and the optimum drift region length (L$_{dr}$) of SOI (Silicon-On-Insulator) pn diodes are derived in terms of the doping concentration and the thickness of the n- drift region and the buried oxide thickness. The optimum L$_{dr}$ is obtained from the condition that the breakdown voltage of the vertical electric field of n+n- junction equals to the of the lateral electric field of n+n-p+ junction. Analytical results agree reasonably with the numerical simulations using PISCESII.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.612-615
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• 2004

A high-voltage generator is used to program the anti-fuse of the semiconductor chip. A new high-voltage generator consists of PN diodes and new stack type capacitors. An oscillator supply pulses to the high-voltage generator. The pulse period of the oscillator is delayed by controlling gate-voltage of the MOS. The pulse period is about 27ns, therefore the pulse frequency is about 37MHz. The threshold voltage of PN diode is about 0.8V. The capacitance of new stack type capacitor is about 4pF. The output voltage of the new high-voltage generator is about 7.9V and its current capacity is about $488{\mu}$A.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.6
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• pp.1-5
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• 2009

Analytical expressions for breakdown voltage and specific on-resistance of 6H-SiC PN diodes have been derived successfully by extracting an effective ionization coefficient from ionization coefficients for electron and hole in 6H-SiC. The breakdown voltages induced from our analytical model are compared with experimental results. The variation of specific on-resistance as a function of doping concentration is also compared with the one reported previously. Good fits with experimental results are found for the breakdown voltage within 10% in error for the doping concentration in the range of $10^{15}{\sim}10^{18}cm^{-3}$. The analytic results show good agreement with the numerical data for the specific on-resistance in the region of $5{\times}10^{15}{\sim}10^{16}cm^{-3}$.

• Journal of the Semiconductor & Display Technology
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• v.16 no.2
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• pp.39-43
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• 2017

It was confirmed that the silicon thin films fabricated on the p-Si (100) substrates by using DIPAS (DiIsoPropylAminoSilane) and TDMA-Sb (Tris-DiMethylAminoAntimony) sources by RPCVD method were amorphous and n-type silicon. The fabricated amorphous n-type silicon films had electron carrier concentrations and electron mobilities ranged from $6.83{\times}10^{18}cm^{-3}$ to $1.27{\times}10^{19}cm^{-3}$ and from 62 to $89cm^2/V{\cdot}s$, respectively. The ideality factor of the pn junction diode fabricated on the p-Si (100) substrate was about 1.19 and the efficiency of the fabricated pn solar cell was 10.87%.

• Journal of IKEEE
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• v.26 no.2
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• pp.306-312
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• 2022

We investigated electrical properties and deep level traps in 4H-SiC merged PiN Schottky (MPS) diodes with different barrier heights by different PN ratios and metallization annealing temperatures. The barrier heights of MPS diodes were obtained in IV and CV characteristics. The leakage current increased with the lowering barrier height, resulting in 10 times larger current. Additionally, the deep level traps (Z_1/2 and RD_1/2) were revealed by deep level transient spectroscopy (DLTS) measurement in four MPS diodes. Based on DLTS results, the trap energy levels were found to be shallow level by 22~28% with lower barrier height It could confirm the dependence of the defect level and concentration determined by DLTS on the Schottky barrier height and may lead to incorrect results regarding deep level trap parameters with small barrier heights.

• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1947-1949
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• 1999

Carrier lifetime in silicon power devices caused switching delay and excessive power loss at high frequency switching. We studied transient turn-on/turn-off transient characteristics of electron irradiated and proton irradiated silicon pn junction diodes. Both the electron and proton irradiation of power devices have already become a widely used practice to reduce minority carrier lifetime locally[1]. The sample is n+p junction diode, made by ion implantation on a $20\Omega.cm$ p-type wafer. We investigated turn-on/turn-off transient & breakdown voltage characteristics by digital oscilloscope. Our data show that proton irradiated samples show better performance than electron irradiated samples.

• Proceedings of the KIEE Conference
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• 1995.11a
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• pp.348-351
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• 1995

A modified silicon direct bonding method has been developed alloying an intimate contact between grooved and smooth mirror-polished oxide-free silicon wafers. A regular set of grooves was formed during preparation of heavily doped $p^+$-type grid network by oxide-masking und boron diffusion. Void-free bonded interfaces with filing of the grooves were observed by x-ray diffraction topography, infrared, optical. and scanning electron microscope techniques. The presence of regularly formed grooves in bending plane results in the substantial decrease of dislocation over large areas near the interface. Moreover two strongly misoriented waters could be successfully bonded by new technique. Diodes with bonded a pn-junction yielded a value of the ideality factor n about 1.5 and the uniform distribution of series resistance over the whole area of horded pn-structure. The suitability of the modified technique was confirmed by I - V characteristics of power diodes and reversly switched-on dynistor(RSD) with a working area about $12cm^2$. Both devices demonstrated breakdown voltages close to the calculation values.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.3
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• pp.252-259
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• 1990

This paper present new scheme for a Side Wall Masked Isolation(SWAMI) technology which take all the advatages provided by conventional LOCOS process. A new SWAMI process incorporates a sloped sidewall by reactive ion etch and a layer of thin nitride around the side walls such that both intrinsic nitride stress and volume expansion induced stress are greatly reduced. As a fabricate results, a defect-free fully recessed zero bird's beak local oxidation process can be realized by the sloped wall anisotropic oxide isolation. No additional masking step is required. The leakage current of PN diodes of this process were reduced than PN diode of conventional LOCOS process. On the other hand, the edge junction part was larger than the flat juction part in the density of leakage current.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.6
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• pp.367-371
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• 2018

1,200 V class junction barrier schottky (JBS) diodes and schottky barrier diodes (SBD) were simultaneously fabricated on the same 4H-SiC wafer. The resulting diodes were characterized at temperatures from room temperature to 473 K and subsequently compared in terms of their respective I-V characteristics. The parameters deduced from the observed I-V measurements, including ideality factor and series resistance, indicate that, as the temperature increases, the threshold voltage decreases whereas the ideality factor and barrier height increase. As JBS diodes have both Schottky and PN junction structures, the proper depletion layer thickness, $R_{on}$, and electron mobility values must be determined in order to produce diodes with an effective barrier height. The comparison results showed that the JBS diodes exhibit a larger effective barrier height compared to the SBDs.