• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.163-166
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• 1999

In this paper, frequency synthesizer that can be used in IMT-2000 was designed and fabricated using dual loop PLL(Phase Locked Loop). For improving phase noise characteristic Voltage Controlled Oscillator was fabricated using coaxial resonator and eliminated frequency divider using SPD as phase detector and increased open loop gain. Fabricated frequency synthesizer had 1.82㎓ center frequency, 160MHz tuning range and -119.73㏈c/Hz low phase noise characteristic.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.37-40
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• 2003

The 1.63㎓, 2.33㎓ dual-band PLL frequency synthesizer has been developed for applications to the miniature repeater. The miniature dual-band repeater will be used at shopping mall, basements and underground parking lots. The in-loop 1.63㎓, 2.33㎓ dual-band PLL frequency synthesizer has been developed by designing Si BJT VCO and PLL loop circuits with Colpitts. The prototype of 1.63㎓, 2.33㎓ dual-band PLL frequency synthesizer of size 19${\times}$19${\times}$8(mm) has shown operating frequencies of 1.63㎓, 2.33㎓ ranges, RF output of 1dBm(PCS), 1dBm(IMT-2000), phase noise of -100 dBc/Hz(PCS), -95dBc/Hz(IMT-2000) at 10KHz offset, harmonics suppression of -24dB c(PCS), -15dBc(IMT-2000).

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.11
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• pp.1074-1080
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• 2013

The low phase noise and wideband frequency synthesizer has been designed by using YTO. Offset PLL structure is used for reducing a division ratio of feedback loop. The phase noise modeling is applied to optimize loop filter of PLL and YTO module. And DDS is used as reference signal of frequency synthesizer for fine resolution. The fabricated wideband frequency synthesizer has the output frequency of 3.2 GHz to 6.8 GHz, phase noise of -107 dBc/Hz at 10 kHz offset from the carrier and frequency resolution of 1 Hz. The measured phase noise is well agreed with the simulated one.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.137-140
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• 2005

A frequency synthesizer of 10 GHz $\sim$ 11 GHz for FMCW radar is designed and implemented by the form of indirect frequency synthesizer of a single loop structure. The synthesizer uses a high speed digital PLL chip. It is difficult to divide directly by using a program counter of PLL chip because the output frequency of VCO is 10 GHz $\sim$ 11 GHz, so we lower the frequency to 625 MHz $\sim$ 687.5 MHz by using a prescaler, and then divide the frequency by the program counter. The output frequency sweep of VCO from 10 GHz to 11 GHz is measured.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.534-542
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• 2017

This paper presents a fast locking technique for a fractional-N PLL frequency synthesizer. The technique directly measures $K_{VCO}$ on a chip, computes the VCO's target tuning voltage for a given target frequency, and directly sets the loop filter voltage to the target voltage before the PLL begins the normal closed-loop locking process. The closed-loop lock time is significantly minimized because the initial frequency of the VCO are put very close to the desired final target value. The proposed technique is realized and designed for a 4.3-5.3 GHz fractional-N synthesizer in 65 nm CMOS and successfully verified through extensive simulations. The lock time is less than $12.8{\mu}s$ over the entire tuning range. Simulation verifications demonstrate that the proposed method is very effective in reducing the synthesizer lock time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.1
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• pp.54-62
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• 1988

For code division multiple access, a frequency synthesizer of elementary components is necessary in the system application of frequency hopped spread spectrum communication. This paper proposes the model of N-loop PLL frequency synthesizer to be adaptied for generating the output frequency resultes in the frequency hopping pattern and to be easy in practical application of the system. It was analyzed how the frequency divider ratio distribute, what the method to decide frequency divider ratio is and what relationship of bandwidth of BPF and degree of multiple have is also analyzed in order to hop the desired frequency output.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.2
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• pp.402-407
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• 2005

The PLL synthesizer is used in communication system until now because it have several merits, such as broad bandwidth, high accuracy and stability of frequency But it is difficult to use in the third generation mobile communication systems that need frequency hopping at a high speed because of its long frequency hopping time. In this paper, we designed the frequency synthesizer that generate frequencies randomly at a high speed using the DDS technology.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.6
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• pp.599-607
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• 2004

In this paper, using phase locked loop(PLL) synthesizer, we introduce a novel but simple and low cost frequency modulation(FM) circuit of a flat peak frequency deviation fur modulation signal whose frequency covers from outside to inside of the loop-bandwidth of PLL. The FM circuit was basically designed to compensate an amount of feedback of the loop filter in PLL. The circuit also includes the capability of the adjustment of peak frequency deviation and of blocking the intereference with the loop filter. The designed circuit was successfully implemented and showed the flat frequency deviation as expected in the design. In addition, the novel measurement method of the wideband FM modulation index is suggested verified With the suggest measurement, it can be successfully shown the designed circuit has the expected frequency deviation.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.286-288
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• 2007

In this paper, the fast locking PLL Frequency Synthesizer with low phase noise in a 0.18um CMOS process is presented. Its main application IS for the 915MHz ISM band wireless transponder upon the CPFSK (Continuous Phase Frequency Shift Keying) modulation scheme. Frequency synthesizer, which in this paper, is designed based on self-biased techniques and is independent with processing technology when damping factor and bandwidth fixed to most important parameters as operating frequency ratio, broad frequency range, and input phase offset cancellation. The proposed frequecy synthesizer, which is fully-integrated and is in 320M $^{\sim}$ 960MHz of the frequency range with 10MHz of frequency resolution. And its is implemented based on integer-N architecture. Its power consumption is 50mW at 1.8V of supply voltage and core area is $540{\mu}m$ ${\times}$ $450{\mu}m$. The measured phase noises are -117.92dBc/Hz at 10MHz offset, with low settling time less than $3.3{\mu}s$.

• Journal of the Korea Institute of Military Science and Technology
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• v.13 no.5
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• pp.775-784
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• 2010

In this paper we propose a design method of X band frequency hopping synthesizer in terms of phase noise and settling time with DDS driven PLL architecture, which has the advantages of high frequency resolution, fast settling time and small size. In addition, a noble method is proposed to remove the synthesizer output spurious signals due to superposition effect of DDS. The spurious signal which depend on its normalized frequency of DDS, can be dominant if they occur within the PLL loop bandwidth. We verify that the sources of that spurious signals are quasi-amplitude modulation and superposition effect, and suggest that such signals can be eliminated by intentionally creating frequency errors in the developed synthesizer.