• The Journal of the Institute of Internet, Broadcasting and Communication
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• 제12권5호
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• pp.1-9
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• 2012

In this paper, we presents the modeling and implementation of the DDS(Direct Digital synthesizer) driven offset PLL(Pghase Locked Loop) with DAC(Digital Analog Converter) for coarse tune. The PLL synthesizer was designed for minimizing the size and offset frequency and DDS technique was used for ultra low noise and fast lock up time, also DAC was used for coarse tune. The output phase noise was analyzed by superposition theory with the phase noise transfer function and noise source modeling. the phase noise prediction was evaluated by comparing with the measured data. The designed synthesizer has ultra fast lock time within 6 usec and ultra low phase noise performance of -120 dBc/Hz at 10KHz offset frequency.

• Journal of Yeungnam Medical Science
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• 제6권2호
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• pp.217-222
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• 1989

In this study, high frequency oscillatory ventilator was designed and constructed. Using designed by phase-lock loop system, in order to accurately and easily treat both the outlet volume and rpm. A system has been designed and is being evaluated using CD4046A PLL IC. We use this PLL IC for the purpose of motor controls. The device consists of PLL system, pumping mechanism, piston, cylinder, and special crank shaft are required. This system characteristics were as follows : 1) Frequency : 20-1800rpm. 2) Outlet air volume : 1-50cc.

• The Journal of the Korea institute of electronic communication sciences
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• 제7권2호
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• pp.333-339
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• 2012

Global flow of communication is a trend of high speed, digitalization, and high-capacity. Furthermore, spread spectrum method has been dominantly utilized to efficiently use the frequency which is the scarce resource. The PLL (Phase Lock Loop) which is a widely used frequency synthesizer in communication systems has few problems such as status interferences and hence, this study utilized the DDS (Direct Digital Synthesis) which is a digital device that can minimize the problems of PLL for the study on the performance evaluation of high speed frequency hopping system design. We designed a system that practices high speed frequency hopping and interprets improvement of error-rates and evaluated its performance.

• Proceedings of the IEEK Conference
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.955-958
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• 1999

We designed a phase locked loop (PLL), which is applicable to microprocessor clock generation application. The designed PLL has a new simple phase frequency detector (PFD) which eliminate dead-zone and has a good high frequency characteristic. The lock-in range of the designed PLL is 50 MHz ~ 150 MHz at 3.3v power supply voltage. The design is carried out using a 0.6${\mu}{\textrm}{m}$ triple metal CMOS process. The area of the layout is 0.35mm by 0.42mm with 359 transistors.

• Proceedings of the KIEE Conference
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• 대한전기학회 2008년도 추계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.132-135
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• 2008

This paper presents a PLL(Phase Lock Loop) control method for speed control of high speed miniature BLDCM(Brushless DC Motor) using hall sensor. The Proposed PLL based speed control method uses a only phase shift between reference pulse signal according to speed reference and actual pulse signal from hall sensor. It doesn't use any speed calculation, and calculates a direct current reference from phase shift. The current reference is changed to reduce the phase shift between reference and actual pulse. So the actual speed can keep the reference speed. The proposed control scheme is very simple but effective speed control is possible.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제20권4호
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• pp.811-818
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• 2016

A continuous fine-tuning phase locked loop with an additional negative feedback loop has been proposed. When the phase locked loop is out-of-lock, the phase locked loop has a fast locking characteristic using the continuous band-selection loop. When the phase locked loop is near in-lock, the bandwidth is narrowed with the fine loop. The additional negative feedback loop consists of a voltage controlled oscillator, a frequency voltage converter and its internal loop filter. It serves a negative feedback function to the main phase locked loop, and improves the phase noise characteristics and the stability of the proposed phase locked loop. The additional negative feedback loop makes the continuous fine-tuning loop work stably without any voltage fluctuation in the loop filter. Measurement results of the fabricated phase locked loop in $0.18{\mu}m$ CMOS process show that the phase noise is -109.6dBc/Hz at 2MHz offset from 742.8MHz carrier frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 한국정보통신학회 2017년도 춘계학술대회
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• pp.691-693
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• 2017

A novel structure of fast locking phase locked loop (PLL) with time difference detector and Lock status indicator (LSI) is proposed in this paper. Fast locking time is achieved using LSI. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.

• The Transactions of the Korean Institute of Power Electronics
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• 제14권2호
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• pp.112-119
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• 2009

This paper presents a PLL(Phase Lock Loop) approach for effective speed and torque control of high speed miniature BLDCM(Brushless DC Motor) using hall sensor. The proposed speed control method based on PLL uses only a phase shift between reference pulse signal according to speed reference and actual pulse signal from hall sensor. It doesn't use any speed calculation, and calculates a direct current reference from phase shift. The current reference is changed to reduce the phase shift between reference and actual pulse. So the actual speed can keep the reference speed. The proposed control scheme is very simple but effective speed control is possible. In order to obtain a smooth torque production, the reference current is changed using acceleration and deceleration slope. The proposed control scheme is verified by experimental results of the 50W, 40,000[rpm] high speed miniature BLDCM.

• The Bulletin of The Korean Astronomical Society
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• 제31권2호
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• pp.35.1-35.1
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• 2006

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• 제28권11호
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• pp.68-76
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• 2014

This paper presents an offset error compensation algorithm for the accurate phase angle of the grid voltage in single-phase grid-connected inverters. The offset error generated from the grid voltage measurement process cause the fundamental harmonic component with grid frequency in the synchronous reference frame phase lock loop (PLL). As a result, the grid angle is distorted and the power quality in power systems is degraded. In addition, the dq-axis currents in the synchronous reference frame and phase current have the dc component, first and second order ripples compared with the grid frequency under the distorted grid angle. In this paper, the effects of the offset and scaling errors are analyzed based on the synchronous reference frame PLL. Particularly, the offset error can be estimated from the integrator output of the synchronous reference frame PLL and compensated by using proportional-integral controller. Moreover, the RMS (Root Mean Square) function is proposed to detect the offset error component. The effectiveness of the proposed algorithm is verified through simulation and experiment results.