• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.1
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• pp.16-21
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• 2002

In this paper, a dual type PFD(Phase Frequency Detector) for high speed PLL to improve output characteristics using TSPC(True Single Phase Clocking) circuit is proposed. The conventional 3-state PFD has problems with large dead-zone and long delay time. Therefore, it is not applicable to high-speed PLL(Phase-Locked Loop). A dynamic PFD with dynamic CMOS logic circuit is proposed to improve these problems. But, it has the disadvantage of jitter noise due to the variation of the duty cycle. In order to solve the problems of previous PFD, the proposed PFD improves not only the dead zone and duty cycle but also jitter noise and response characteristics by the TSPC circuit and dual structured PFD circuit. The PFD is consists of a P-PFD(Positive edge triggered PFD) and a N-PFD(Negative edge triggered PFD) and improves response characteristics to increase PFD gain. The Hspice simulation is performed to evaluate the performance of proposed PFD. From the experimental results, it has the better dead zone, duty cycle and response characteristics than conventional PFDs.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.1
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• pp.175-181
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• 2005

This paper proposes the fuzzy-PLL control system for fast response time and precision control of automation systems. The conventional PLL has not only a jitter noise caused from such a demerit of the wide dead zone, but also a long delay interval that makes a high speed operation unable. In order to solve the problems, the proposed system, which provides the improvement in terms of the control region in high speed and precision control, first used the fuzzy control method for fast response time and when the error reaches the preset value, used the PLL method designing new PFD for precision control. The new designed multi-PFD improves the dead zone, jitter noise and response characteristics, which is consists of P-PFD(Positive edge triggered PFD) and N-PFD(Negative edge triggered PFD) and can improve response characteristics to increase PFD gain.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.275-278
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• 1999

In this paper, Dual PFD(Phase Frequency Detector) with improved phase locking time is proposed. The proposed PFD consists of positive and negative edge triggered D flip-flop. In order to confirm the characteristics of proposed PFD, HSPICE simulations are performed using a 0.25${\mu}{\textrm}{m}$ CMOS process. As a result of simulations, the proposed PFD has a characteristic of fast phase locking time with dead zone free.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.198-201
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• 2014

The phase frequency detector (PFD) is one of the most important building blocks of a phase locked Loop (PLL). Due to blind-zone problem, the detection range of the PFD is low. The blind zone of a PFD directly depends upon the reset time of the PFD and the pre-charge time of the internal nodes of the PFD. Taking these two parameters into consideration, a PFD is designed to achieve a small blind zone closer to the limit imposed by process-voltage-temperature variations. In this paper an enhanced architecture is proposed for dynamic logic PFD to minimize the blind-zone problem. The techniques used are inverter sizing, transistor reordering and use of pre-charge transistors. The PFD is implemented in 180 nm technology with supply voltage of 1.8 V.

• Proceedings of the Korea Water Resources Association Conference
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• 2006.05a
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• pp.226-230
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• 2006

홍수피해잠재능(Potential Flood Damage: PFD)은 면 개념을 도입함으로써 치수단위구역의 치수특성 및 사회경제적인 가치를 함께 평가할 수 있도록 고안된 지수로 이미 여러 유역에서 시행되고 있는 유역종합 치수계획 사업에서 사용되고 있으나, 몇 가지 중요한 문제점이 꾸준히 제기되어 왔다. 본 연구에서는 우선 다음과 같은 이론적 문제점을 검토하였다. PFD는 처음 제안될 당시 (이하 기존 PFD) '잠재성'과 '위험성'라는 두 가지 요소가 곱해지는(multiplicative) 형태로 구성된 후 '위험성' 요소 안에 '가능성'과 '방어능력'이 더해지는 (additive) 형태를 취하고 있었다. 그러나 본 연구에서는 (이하 수정 PFD) '피해대상', '피해가능성', 그리고 '방어취약성'이 모두 곱해져야 이론적으로 타당함을 제시하였다. 기존 PFD는 '방어취약성'이 0의 값, 즉 홍수에 대한 완전방어를 의미하는 값에 가까워져도 PFD 값이 0에 수렴하지 않는 반면, 수정 PFD는 위의 경우 홍수 피해잠재능이 0에 수렴하는 것을 요소별 시나리오 모의를 통해서 확인할 수 있었다. 두 번째로 본 연구에서는 PFD를 이용하여 유역의 목표치수안전도 설정 방안을 제시하였다. PFD의 물리적인 의미가 무차원화 된 피해량 임을 전제로, 피해대상으로부터 목표방어율을 설정한 후 이에 해당하는 목표방어취약성을 계산하는 절차를 전개하였다. 추후 이 방법을 실제 자료에 적용하여 검증하는 연구가 이어져야 할 것이다.

• Proceedings of the KIEE Conference
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• 1999.11c
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• pp.742-744
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• 1999

In this paper, a new precharge type PFD for fast locking time of PLL is suggested. It is realized by inserting NMOS transistor and inverter into the precharge part of PFD for isolating the reset of the Up signal from the feedback signal. The new precharge type PFD generates the Up signal while the feedback signal is fixed at a high level. Therefore the new PFD output is increased than the conventional precharge type PFD output. As a result of the increased PFD output, fast locking of PLLs is achieved. Additionally, with control the falling time of the inverter, the dead-zone is reduced and the jitter characteristics are improved. The whole characteristics of PFD and PLL are simulated by using HSPICE. Simulation results show that the dead-zone is 20ps and the locking time of PLL using the new PFD is 38ns at the 350MHz frequency of referecne signal. This value is quite small compared with conventional PFD.

• Journal of Korea Water Resources Association
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• v.57 no.1
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• pp.21-33
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• 2024

Recently, the patterns of climate change-induced disasters have become more diverse and extensive. To develop an effective flood control plan, Korea has incorporated the concept of Potential Flood Damage (PFD) into the Long-Term Comprehensive Water Resources Plan to assess flood risk. However, concerns regarding the PFD have prompted numerous studies. Previous research primarily focused on modifying and augmenting the PFD index or introducing new indices. This study aims to enhance the existing flood control safety evaluation method by utilizing a flood risk map that incorporates risk indices, specifically focusing on the Yeong-Seomjin river basin. The study introduces three main evaluation approaches: risk and potential analysis, PFD and flood management level analysis, and flood control safety evaluation. The proposed improved evaluation method is expected to be instrumental in evaluating various flood control safety measures and formulating flood control plans.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.271-274
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• 2001

In this paper, we propose a charge pump phase-locked loop (PLL) with multi-PFD which is composed of a sequential phase frequency detector(PFD) and a precharge PFD. When the Phase difference is within - $\pi$ ∼ $\pi$ , operation frequency can be increased by using precharge PFD. When the phase difference is larger than │ $\pi$ │, acquisition time can be shorten by the additional control circuit with increased charge pump current. Therefore a high frequency operation, a fast acquisition and an unlimited error detection range can be achieved.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3088-3090
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• 2000

In this paper, we introduce a charge pump PLL architecture which employs precharge phase frequency detector(PFD) and sequential PFD to achieve high frequency operation and fast acquisition. Operation frequency is increased by using precharge PFD when the phase difference is within -${\pi}\;{\sim}\;{\pi}$ and acquisition time is shortened by using sequential PFD and increased charge pump current when the phase difference is larger than |${\pi}$|. SO error detection range of proposed PLL structure is not limited to -${\pi}\;{\sim}\;{\pi}$. By virtue of this multi-phase frequency detector structure, the maximum operating frequency of 423MHz at 2.5V and faster acquisition were achieved by simulation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.385-388
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• 2003

In this paper, a D-Latch is replaced by a memory cell on the proposed PFD to improve response tine by reducing reset me. The PFD has been simulated using HSPICE with a Hynix 0.35um CMOS process to prove the performance improvement.