1 |
Harufusa Kondoh et al., 'A 1.5-V 250-MHz to 3.0-V 622-MHz Operation CMOS Phase-Locked Loop with Precharge Type Phase-Frequency Detector,' IEICE Trans Electron., Vol. E78 C. No. 4, pp. 381-388, April 1995
|
2 |
Jung-Dong Cho, et al., 'A High-Speed, Low-Power Phase Frequency Detector and Charge-Pump Circuits for High Frequency Phase-Locked Loops,' IEICE Trans Fundamentals, Vol. E82-A, No. 11, pp. 2514-2520, Nov. 1999
|
3 |
Y. Sumi, et al., 'Dead-zoneless PLL Frequency Synthesizer by Hybrid Phase Detectors,' in Proc. IEEE JSSC, Vol. 4, pp. 410-414, July 1999
|
4 |
Tae-Hun Kim and Beomsup Kim, 'Dual-loop Digital for Adaptive Clock Recovery,' in Proc. IEEE JSSC, Vol. 4, pp. 410-414, July 1999
|
5 |
William F. Egan, Frequency Synthesis by Phase Lock, 2nd ed., John Willey & Sons, Inc., 2000
|
6 |
Henrik O. Johansson, 'A Simple Precharged CMOS Phase Frequency Detector,' IEEE JSSC, Vol. 33, No. 2, pp. 295-299, Feb. 1998
|
7 |
Sang-O Jeon, et al., 'Phase/frequency Detectors for High-Speed PLL Applications,' Electronics Letters, Vol. 34, No. 22, pp. 2120-2121, Oct. 1998
DOI
ScienceOn
|
8 |
J. Yuan and C. Svensson, 'New Single-Clock CMOS Latches and Flipflops with Improved Speed and Power Savings,' IEEE JSSC, Vol.32, No. 1, pp. 62-69, Jan. 1997
|
9 |
R. E. Best, Phase-Locked Loops Theory, Design, and Applications, 3rd ed., New York : McGraw-Hill, 1997
|