• Journal of the Semiconductor & Display Technology
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• v.17 no.4
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• pp.16-20
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• 2018

Graphene is attracting attention due to its outstanding properties as line material for next-generation semiconductor. Graphene pattern technology is essential to apply graphene line. Selective graphene oxide reduction as one of graphene pattern method does not require a substrate thereby a high flexibility device can be applied. Particularly, the method using photon energy has advantages of short process time and environment friendly. In this review, we introduce the photocatalytic method and the photo-thermal energy conversion method using photon energy in the selective reduction process of graphene oxides.

• Journal of the Semiconductor & Display Technology
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• v.21 no.3
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• pp.22-25
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• 2022

Metal oxide semiconductor (MOS) based on spray-pyrolysis deposition technique has attracted large attention due to simple and low-cost processibility while preserving their intrinsic optical and electrical characteristics. However, their high process temperature limits practical applications. Here, we demonstrated the nc-ZnO/ZnO field-effect transistors (FETs) via spray-pyrolysis as incorporating ZnO nanocrystalline nanoparticles into typical ZnO precursor. The nc-ZnO/ZnO FETs exhibit good quality of electrical properties. Our experiments reveal that nc-ZnO in active layer enhance electrical characteristics.

• Journal of the Semiconductor & Display Technology
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• v.22 no.1
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• pp.78-82
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• 2023

Metal oxide semiconductor (MOS) adapting spray-pyrolysis deposition technique has drawn large attention based on their high quality of intrinsic and electrical properties in addition to simple and low-cost processibility. To fully utilize the merits of MOS field-effect transistors (FETs) , transparency, it is important to understand the instability behaviors of FETs under illumination. Here, we studied the photo-induced properties of nc-ZnO/ZnO field-effect transistors (FETs) based on spray-pyrolysis under illumination which incorporating ZnO nanocrystalline nanoparticles into typical ZnO precursor. Our experiments reveal that nc-ZnO in active layer suppressed the light instabilities of FETs.

• Journal of the Semiconductor & Display Technology
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• v.11 no.4
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• pp.1-6
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• 2012

Keeping the polarization direction of the projection light unchanged is of crucial importance for high quality of images on a double-screen 3D projection display system. It has been found that the deposition of oxide layers on the surfaces of scattering polarizer film results in an improvement of polarization maintenance property of the film. The secondary image formed on the front screen by the light scattered from the rear screen decreases by 30% through the application of oxide layers on both surfaces of the screen. Since the oxide layer can also be used as an anti-reflection (AR) coating of the film, this method is very effective for the projection display applications.

• Journal of the Korean Chemical Society
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• v.54 no.4
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• pp.380-386
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• 2010

We have investigated the growth kinetics of Al oxide film by anodization in sulfuric acid solution and the electronic properties of this film using electrochemical impedance spectroscopy. Al oxide film consisted $Al_2O_3$ was grown based on the point defect model and shown the eclctronic properties of n-type semiconductor.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.100-106
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• 2010

The impact of surface quantization on device parameters of a Si metal oxide semiconductor (MOS) capacitor has been analyzed in the present work. Variation of conduction band bending, position of discrete energy states, variation of surface potential, and the variation of inversion carrier concentration at charge centroid have been analyzed for different gate voltages, substrate doping concentrations and oxide thicknesses. Oxide thickness calculated from the experimental C-V data of a MOS capacitor is different from the actual oxide thickness, since such data include the effect of surface quantization. A correction factor has been developed considering the effect of charge centroid in presence of surface quantization at strong inversion and it has been observed that the correction due to surface quantization is crucial for highly doped substrate with thinner gate oxide.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.2
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• pp.76-82
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• 2003

The robust stack storage node and sufficient cell capacitance for high performance is indispensable for 90 nm DRAM capacitor. For the first time, we successfully demonstrated MIS capacitor process integration for 90 nm DRAM technology. Novel cell layout and integration technology of 90 nm DRAM capacitor is proposed and developed, and it can be extended to the next generation DRAM. Diamond-shaped OCS with 1.8 um stack height is newly developed for large capacitor area with better stability. Furthermore, the novel $Al_2O_3/HfO_2$ dielectric material with equivalent oxide thickness (EOT) of 25 ${\AA}$ is adopted for obtaining sufficient cell capacitance. The reliable cell capacitance and leakage current of MIS capacitor is obtained with ~26 fF/cell and < 1 fA/ceil by $Al_2O_3/HfO_2$ dielectric material, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.243-246
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• 2004

W CMP 공정에서 abrasive 의 size 및 shape 에 따른 CMP 거동에 대해 관찰하였으며, 주요 제거 막질인 W 막질과 stopping layer 로 사용되는 Oxide 막질에 대한 압력(P)과 상대 속도(V) 영향성을 관찰하였다. CMP 제거량이 입자의 size 변화에 의존한다는 기존의 이론과는 달리 응집도(aggregate ratio) 변화가 주요 변수임을 밝혀 내었다. 한편, 각 막질에 대한 P,V 영향성 평가를 통해, 변형된 Prestonian equation 이 abrasive size 및 shape 에 상관없이 W 막질의 제거 거동을 설명하는데 중요한 역할을 수행함을 보였다. 그렇지만, W CMP 공정에서 stopping layer 로 사용되는 oxide 막질의 거동을 설명하는 데에는 어려움이 있었으며, 특히 P,V 에 의한 비선형적 removal rate(RR) 거동발생으로 인해 기존의 이론치와는 많은 차이를 나타내었다. 또한, abrasive size 와 shape 에 따라서도 복잡한 거동을 나타낸다.

• Journal of Sensor Science and Technology
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• v.7 no.1
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• pp.73-82
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• 1998

In silicon surface micro-machining, the newly developed GPE(gas-phase etching) process was verified as a very effective method for the release of highly compliant micro-structures. The developed GPE system with anhydrous HF gas and $CH_{3}OH$ vapor was characterized and the selective etching properties of sacrificial layers to release silicon micro-structures were discussed. P-doped polysilicon and SOI(silicon on insulator) substrate were used as a structural layer and TEOS(tetraethyorthdsilicate) oxide, thermal oxide and LTO(low temperature oxide) as a sacrificial layer. Compared with conventional wet-release, we successfully fabricated micro-structures with virtually no process-induced striction and residual product.

• Korean Journal of Materials Research
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• v.28 no.1
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• pp.32-37
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• 2018

We report on the efficient detection of NO gas by an all-oxide semiconductor p-n heterojunction diode structure comprised of n-type zinc oxide (ZnO) nanorods embedded in p-type copper oxide (CuO) thin film. The CuO thin film/ZnO nanorod heterostructure was fabricated by directly sputtering CuO thin film onto a vertically aligned ZnO nanorod array synthesized via a hydrothemal method. The transport behavior and NO gas sensing properties of the fabricated CuO thin film/ZnO nanorod heterostructure were charcterized and revealed that the oxide semiconductor heterojunction exhibited a definite rectifying diode-like behavior at various temperatures ranging from room temperature to $250^{\circ}C$. The NO gas sensing experiment indicated that the CuO thin film/ZnO nanorod heterostructure had a good sensing performance for the efficient detection of NO gas in the range of 2-14 ppm under the conditions of an applied bias of 2 V and a comparatively low operating temperature of $150^{\circ}C$. The NO gas sensing process in the CuO/ZnO p-n heterostructure is discussed in terms of the electronic band structure.