• Bulletin of the Korean Chemical Society
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• 제35권8호
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• pp.2505-2511
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• 2014

Indium oxide nanocrystals ($In_2O_3$ NCs) with sizes of 5.5 nm-10 nm were synthesized by hot injection of the mixture precursors, indium acetate and oleic acid, into alcohol solution (1-octadecanol and 1-octadecence mixture). Field emission transmission electron microscopy (FE-TEM), High resolution X-Ray diffraction (X-ray), Nuclear magnetic resonance (NMR), and Fourier transform infrared spectroscopy (FT-IR) were employed to investigate the size, surface molecular structure, and crystallinity of the synthesized $In_2O_3$ NCs. When covered by oleic acid as a capping group, the $In_2O_3$ NCs had a high crystallinity with a cubic structure, demonstrating a narrow size distribution. A high mobility of $2.51cm^2/V{\cdot}s$ and an on/off current ratio of about $1.0{\times}10^3$ were observed with an $In_2O_3$ NCs thin film transistor (TFT) device, where the channel layer of $In_2O_3$ NCs thin films were formed by a solution process of spin coating, cured at a relatively low temperature, $350^{\circ}C$. A size-dependent, non-monotonic trend on electron mobility was distinctly observed: the electron mobility increased from $0.43cm^2/V{\cdot}s$ for NCs with a 5.5 nm diameter to $2.51cm^2/V{\cdot}s$ for NCs with a diameter of 7.1 nm, and then decreased for NCs larger than 7.1 nm. This phenomenon is clearly explained by the combination of a smaller number of hops, a decrease in charging energy, and a decrease in electronic coupling with the increasing NC size, where the crossover diameter is estimated to be 7.1 nm. The decrease in electronic coupling proved to be the decisive factor giving rise to the decrease in the mobility associated with increasing size in the larger NCs above the crossover diameter.

• 마이크로전자및패키징학회지
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• 제25권2호
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• pp.49-53
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• 2018

최근 유연 소자, 투명 소자, MEMS 소자와 같은 다양한 소자를 결합하는 시스템 집적화 기술이 많이 개발되고 있다. 이러한 다종 소자 시스템 제조 기술의 핵심 공정은 칩 또는 웨이퍼 레벨의 접합 공정, 기판 연삭 공정, 그리고 박막 기판 핸들링 기술이라 하겠다. 본 연구에서는 Si 기판 연삭 공정이 투명 박막 트랜지스터나 유연 전극 소재로 적용되는 산화주석 박막의 전기적 성질에 미치는 영향을 분석하였다. Si 기판의 두께가 얇아질수록 Si d-spacing은 감소하였고, Si 격자 내에 strain이 발생하였다. 또한, Si 기판의 두께가 얇아질수록 산화주석 박막 내 캐리어 농도가 감소하여 전기전도도가 감소하였다. 얇은 산화 주석 박막의 경우 전기전도도는 두꺼운 산화 주석 박막보다 낮았으며 Si 기판의 두께에 의해 크게 변하지 않았다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.1334_1335
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• 2009

In this paper we have presented recent studies concerning the high performance oxide thin film transistor (TFT) with a-IGZO channel and $ZrO_2$ gate dielectrics. The a-IGZO TFT is fully fabricated at room-temperature without any thermal treatments. The $ZrO_2$ is one of the most promising high-k materials with high capacitance originated from the high dielectric constant. The a-IGZO TFT with $ZrO_2$ shows high performance exhibiting high field effect mobility of $39.82\;cm^2$/Vs and high on-current of 2.52 mA at 10V.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.707-710
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• 2006

Zinc oxide (ZnO) is typically highly doped n-type semiconductor. To be used for thin-film transistor (TFT) devices, carrier concentration must be controlled precisely. We studied characteristics of ZnO grown by MOCVD at temperatures between $200^{\circ}C$ and $400^{\circ}C$. We found that hydrogen incorporated during growth plays important role in determining carrier density.

• Transactions on Electrical and Electronic Materials
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• 제16권4호
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• pp.187-189
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• 2015

A charge-trap flash (CTF) thin film transistor (TFT) memory is proposed at a low-temperature process (≤ 450℃). The memory cell consists of a sputtered oxide-nitride-oxide (ONO) gate dielectric and Schottky barrier (SB) source/drain (S/D) junctions using nickel silicide. These components enable the ultra-low-temperature process to be successfully achieved with the ONO gate stacks that have a substrate temperature of room temperature and S/D junctions that have an annealing temperature of 200℃. The silicidation process was optimized by measuring the electrical characteristics of the Ni-silicided Schottky diodes. As a result, the Ion/Ioff current ratio is about 1.4×10⁵ and the subthreshold swing and field effect mobility are 0.42 V/dec and 14 cm²/V·s at a drain voltage of −1 V, respectively.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 하계학술대회 논문집 B
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• pp.1292-1294
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• 1993

This paper proposes a new structure of polycrystalline silicon(poly-Si) thin film transistor(TFT) having a thick gate-oxide below the gate edge. The new structure is fabricated by the gate re-oxidation in wet ambient. It is shown that the thick gate-oxide below the gate edge is effective in reducing the leakage current and the gate-drain overlap capacitance. We have simulated this device by using the SSUPREM4 process simulator and the SPISCES-2B device simulator. As a simulation result it is found that the new structure provides a low tentage current less than 0.2 pA and achieves a on/off ratio as high as $5{\times}10^7$.

• 한국전기전자재료학회논문지
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• 제36권6호
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• pp.588-593
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• 2023

The advantage of OTFT technology is that large-area circuits can be manufactured on flexible substrates using a low-cost solution process such as inkjet printing. Compared to silicon-based inorganic semiconductor processes, the process temperature is lower and the process time is shorter, so it can be widely applied to fields that do not require high electron mobility. Materials that have utility as electrode materials include carbon that can be solution-processed, transparent carbon thin films, and metallic nanoparticles, etc. are being studied. Recently, a technology has been developed to facilitate charge injection by coating the surface of the Al electrode with solution-processable titanium oxide (TiOx), which can greatly improve the performance of OTFT. In order to commercialize OTFT technology, an appropriate method is to use a complementary circuit with excellent reliability and stability. For this, insulators and channel semiconductors using organic materials must have stability in the air. In this study, carbon-doped Mo (MoC) thin films were fabricated with different graphite target power densities via unbalanced magnetron sputtering (UBM). The influence of graphite target power density on the structural, surface area, physical, and electrical properties of MoC films was investigated. MoC thin films deposited by the unbalanced magnetron sputtering method exhibited a smooth and uniform surface. However, as the graphite target power density increased, the rms surface roughness of the MoC film increased, and the hardness and elastic modulus of the MoC thin film increased. Additionally, as the graphite target power density increased, the resistivity value of the MoC film increased. In the performance of an organic thin film transistor using a MoC gate electrode, the carrier mobility, threshold voltage, and drain current on/off ratio (I_on/I_off) showed 0.15 cm²/V·s, -5.6 V, and 7.5×10⁴, respectively.

• 반도체디스플레이기술학회지
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• 제13권3호
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• pp.35-38
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• 2014

Flat panel displays fabricated on glass substrate use amorphous Si for data processing circuit. Recent progress in display technology requires a new material to replace the amorphous Si, and ZnO is a good candidate. ZnO is a wide bandgap (3.3 eV) semiconductor with high mobility and good optical transparency. ZnO is usually grown by sputtering using ZnO ceramic target. However, ceramic target is more expensive than metal target, and making large area target is very difficult. In this work we studied characteristics of ZnO thin-film transistor grown by rf sputtering using Zn metal target and $CO_2$. ZnO film was grown at $450^{\circ}C$ substrate temperature, with -70 V substrate bias voltage applied. By using these methods, our ZnO TFT showed $5.2cm^2/Vsec$ mobility, $3{\times}10^6$ on-off ratio, and -7 V threshold voltage.

• Journal of Electrical Engineering and Technology
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• 제12권6호
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• pp.2353-2358
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• 2017

A femtosecond laser pre-annealing process based on indium zinc oxide (IZO) thin-film transistors (TFTs) is fabricated. We demonstrate a stable pre-annealing process to analyze surface structure change of thin films, and we maintain electrical stability and improve electrical performance. Furthermore, dynamic electrical characteristics of the IZO TFTs were investigated. Femtosecond laser pre-annealing process-based IZO TFTs exhibit a field-effect mobility of $3.75cm^2/Vs$, an $I_{on}/I_{off}$ ratio of $1.77{\times}10^5$, a threshold voltage of 1.13 V, and a subthreshold swing of 1.21 V/dec. And the IZO-based inverter shows a fast switching behavior response. From this study, IZO TFTs from using the femtosecond laser annealing technique were found to strongly affect the electrical performance and charge transport dynamics in electronic devices.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.471-471
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• 2013

Highly stable and high performance amorphous oxide semiconductor thin film transistors (TFTs) were fabricated using 4-mercaptophenol (4MP) doped ZnO by atomic layer deposition (ALD). The 4 MP concentration in ZnO films were varied from 1.7% to 5.6% by controlling Zn: 4MP pulses. The carrier concentrations in ZnO thin films were controlled from $1.017{\times}10^{20}$/$cm^3$ to $2,903{\times}10^{14}$/$cm^3$ with appropriate amount of 4MP doping. The 4.8% 4MP doped ZnO TFT revealed good device mobility performance of $8.4cm^2V-1s-1$ and on/off current ratio of $10^6$. Such 4MP doped ZnO TFTs were stable under ambient conditions for 12 months without any apparent degradation in their electrical properties. Our result suggests that 4 MP doping can be useful technique to produce more reliable oxide semiconductor TFT.