• Title/Summary/Keyword: Oxide Semiconductor

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Surface Preparation of III-V Semiconductors

  • Im, Sang-U
    • Proceedings of the Korean Vacuum Society Conference
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    • 2015.08a
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    • pp.86.1-86.1
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    • 2015
  • As the feature size of Si-based semiconductor shrinks to nanometer scale, we are facing to the problems such as short channel effect and leakage current. One of the solutions to cope with those issues is to bring III-V compound semiconductors to the semiconductor structures, because III-V compound semiconductors have much higher carrier mobility than Si. However, introduction of III-V semiconductors to the current Si-based manufacturing process requires great challenge in the development of process integration, since they exhibit totally different physical and chemical properties from Si. For example, epitaxial growth, surface preparation and wet etching of III-V semiconductors have to be optimized for production. In addition, oxidation mechanisms of III-V semiconductors should be elucidated and re-growth of native oxide should be controlled. In this study, surface preparation methods of various III-V compound semiconductors such as GaAs, InAs, and GaSb are introduced in terms of i) how their surfaces are modified after different chemical treatments, ii) how they will be re-oxidized after chemical treatments, and iii) is there any effect of surface orientation on the surface preparation and re-growth of oxide. Surface termination and behaviors on those semiconductors were observed by MIR-FTIR, XPS, ellipsometer, and contact angle measurements. In addition, photoresist stripping process on III-V semiconductor is also studied, because there is a chance that a conventional photoresist stripping process can attack III-V semiconductor surfaces. Based on the Hansen theory various organic solvents such as 1-methyl-2-pyrrolydone, dimethyl sulfoxide, benzyl alcohol, and propylene carbonate, were selected to remove photoresists with and without ion implantation. Although SPM and DIO3 caused etching and/or surface roughening of III-V semiconductor surface, organic solvents could remove I-line photoresist without attack of III-V semiconductor surface. The behavior of photoresist removal depends on the solvent temperature and ion implantation dose.

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A Study on Improvement and Degradation of Si/SiO2 Interface Property for Gate Oxide with TiN Metal Gate

  • Lee, Byung-Hyun;Kim, Yong-Il;Kim, Bong-Soo;Woo, Dong-Soo;Park, Yong-Jik;Park, Dong-Gun;Lee, Si-Hyung;Rho, Yong-Han
    • Transactions on Electrical and Electronic Materials
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    • v.9 no.1
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    • pp.6-11
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    • 2008
  • In this study, we investigated effects of hydrogen annealing (HA) and plasma nitridation (PN) applied in order to improve $Si/SiO_2$ interface characteristics of TiN metal gate. In result, HA and PN showed a positive effect decreasing number of interface state $(N_{it})$ respectively. After FN stress for verifying reliability, however, we identified rapid increase of $N_{it}$ for TiN gate with HA, which is attributed to hydrogen related to a change of $Si/SiO_2$ interface characteristic. In contrast to HA, PN showed an improved Nit and gate oxide leakage characteristic due to several possible effects, such as blocking of Chlorine (Cl) diffusion and prevention of thermal reaction between TiN and $SiO_2$.

Breakdown Voltage and On-resistance Characteristics of N-channel EDMOS with Dual Work Function Gate (이중 일함수 구조를 적용한 N-채널 EDMOS 소자의 항복전압 및 온-저항 특성)

  • Kim, Min-Sun;Baek, Ki-Ju;Kim, Yeong-Seuk;Na, Kee-Yeol
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.25 no.9
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    • pp.671-676
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    • 2012
  • In this paper, TCAD assessment of 30-V class n-channel EDMOS (extended drain metal-oxide-semiconductor) transistors with DWFG (dual work function gate) structure are described. Gate of the DWFG EDMOS transistor is composed of both p- and n-type doped region on source and drain side. Additionally, lengths of p- and n-type doped gate region are varied while keeping physical channel length. Two-dimensional device structures are generated trough TSUPREM-4 and their electrical characteristics are investigated with MEDICI. The DWFG EDMOS transistor shows improved electrical characteristics than conventional device - i.e. higher transconductance ($g_m$), better drain output current ($I_{ON}$), reduced specific on-resistances ($R_{ON}$) and higher breakdown characteristics ($BV_{DSS}$).

Field Effect Transistors for Biomedical Application (전계효과트랜지스터의 생명공학 응용)

  • Sohn, Young-Soo
    • Applied Chemistry for Engineering
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    • v.24 no.1
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    • pp.1-9
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    • 2013
  • As the medical paradigm is changing from disease treatment to disease prevention and an early diagonosis, the demand to develop techniques for the detection of minute concentrations of biomolecules is increasing. Among the various techniques to sense the minute concentration of biomolecules, the biosensors utilizing the matured semiconductor techniques are presented here. To understand such biosensors, the structure and working principle of a MOSFET (Metal-oxide-semiconductor field-effect transistor) which is the basic semiconductor device is firstly introduced, and then the ISFET (Ion sensitive FET), BioFET (Biologically modified FET), Nanowire FET, and IFET (Ionic FET) are introduced, and their applications to biomedical fields are discussed.

Device Optimization of N-Channel MOSFETs with Lateral Asymmetric Channel Doping Profiles

  • Baek, Ki-Ju;Kim, Jun-Kyu;Kim, Yeong-Seuk;Na, Kee-Yeol
    • Transactions on Electrical and Electronic Materials
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    • v.11 no.1
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    • pp.15-19
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    • 2010
  • In this paper, we discuss design considerations for an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with a lateral asymmetric channel (LAC) doping profile. We employed a $0.35\;{\mu}m$ standard complementary MOSFET process for fabrication of the devices. The gates to the LAC doping overlap lengths were 0.5, 1.0, and $1.5\;{\mu}m$. The drain current ($I_{ON}$), transconductance ($g_m$), substrate current ($i_{SUB}$), drain to source leakage current ($i_{OFF}$), and channel-hot-electron (CHE) reliability characteristics were taken into account for optimum device design. The LAC devices with shorter overlap lengths demonstrated improved $I_{ON}$ and $g_m$ characteristics. On the other hand, the LAC devices with longer overlap lengths demonstrated improved CHE degradation and $I_{OFF}$ characteristics.

In-situ Process Monitoring Data from 30-Paired Oxide-Nitride Dielectric Stack Deposition for 3D-NAND Memory Fabrication

  • Min Ho Kim;Hyun Ken Park;Sang Jeen Hong
    • Journal of the Semiconductor & Display Technology
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    • v.22 no.4
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    • pp.53-58
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    • 2023
  • The storage capacity of 3D-NAND flash memory has been enhanced by the multi-layer dielectrics. The deposition process has become more challenging due to the tight process margin and the demand for accurate process control. To reduce product costs and ensure successful processes, process diagnosis techniques incorporating artificial intelligence (AI) have been adopted in semiconductor manufacturing. Recently there is a growing interest in process diagnosis, and numerous studies have been conducted in this field. For higher model accuracy, various process and sensor data are required, such as optical emission spectroscopy (OES), quadrupole mass spectrometer (QMS), and equipment control state. Among them, OES is usually used for plasma diagnostic. However, OES data can be distorted by viewport contamination, leading to misunderstandings in plasma diagnosis. This issue is particularly emphasized in multi-dielectric deposition processes, such as oxide and nitride (ON) stack. Thus, it is crucial to understand the potential misunderstandings related to OES data distortion due to viewport contamination. This paper explores the potential for misunderstanding OES data due to data distortion in the ON stack process. It suggests the possibility of excessively evaluating process drift through comparisons with a QMS. This understanding can be utilized to develop diagnostic models and identify the effects of viewport contamination in ON stack processes.

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Passivation property of Al2O3 thin film for the application of n-type crystalline Si solar cells (N-type 결정질 실리콘 태양전지 응용을 위한 Al2O3 박막의 패시베이션 특성 연구)

  • Jeong, Myung-Il;Choi, Chel-Jong
    • Journal of the Korean Crystal Growth and Crystal Technology
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    • v.24 no.3
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    • pp.106-110
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    • 2014
  • The passivation property of $Al_2O_3$ thin film formed using atomic layer deposition (ALD) for the application of crystalline Si solar cells was investigated using microwave photoconductance decay (${\mu}$-PCD). After post-annealing at $400^{\circ}C$ for 5 min, $Al_2O_3$ thin film exhibited the structural stability having amorphous nature without the interfacial reaction between $Al_2O_3$ and Si. The post-annealing at $400^{\circ}C$ for 5 min led to an increase in the relative effective lifetime of $Al_2O_3$ thin film. This could be associated with the field effective passivation combined with surface passivation of textured Si. The capacitance-voltage (C-V) characteristics of the metal-oxide-semiconductor (MOS) with $Al_2O_3$ thin film post-annealed at $400^{\circ}C$ for 5 min was carried out to evaluate the negative fixed charge of $Al_2O_3$ thin film. From the relationship between flatband voltage ($V_{FB}$) and equivalent oxide thickness (EOT), which were extracted from C-V characteristics, the negative fixed charge of $Al_2O_3$ thin film was calculated to be $2.5{\times}10^{12}cm^{-2}$, of which value was applicable to the passivation layer of n-type crystalline Si solar cells.

The Effects of Electrode Materials on the Electrical Properties of $Ta_2O_5$ Thin Film for DRAM Capacitor (DRAM 커패시터용 $Ta_2O_5$ 박막의 전기적 특성에 미치는 전극의존성)

  • Kim, Yeong-Wook;Gwon, Gi-Won;Ha, Jeong-Min;Kang, Chang-Seog;Seon, Yong-Bin;Kim, Yeong-Nam
    • Korean Journal of Materials Research
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    • v.1 no.4
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    • pp.229-235
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    • 1991
  • A new electrode material for $Ta_2O_5$ capacitor was developed to obtain both high dielectric constant and improved electrical properties for use in DRAM. High leakage current and low breakdown field of as-deposited $Ta_2O_5$ film on Si is due to the reduction of $Ta_2O_5$ by silicon at $Ta_2O_5$/electrode interface. $Dry-O_2$ anneal improves the electrical properties of $Ta_2O_5$ capacitor with Si electrode, but it thickens the interfacial oxide and lowers the dielectric constant, subsequently. $Ta_2O_5$ capacitor with TiN exectrode shows better electrical properties and higher dielectric constant than post heat treated $Ta_2O_5$ film on Si. No interfacial oxide layer at $Ta_2O_5$/TiN interface suggests that there\`s no Interaction between $Ta_2O_5$ and electrode. TiN is a adequate electrode material for $Ta_2O_5$ capacitor.

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Experimental fabrication and analysis on the double injection semiconductor switching devices (반도체 DI swiching 소자의 시작과 특성에 관한 실험적 고찰)

  • 성만영;정세진;임경문
    • Electrical & Electronic Materials
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    • v.4 no.2
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    • pp.159-174
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    • 1991
  • 이중주입효과에 의한 고내압 반도체 스위칭소자의 설계 제작에 촛점을 맞추어 Injection Gate구조와 MOS Gate 구조로 시료소자를 제작해 그 특성을 검토하고 Electrical Switching 및 Oxide막에서의 Breakdown현상에 의한 문제점을 해결해 보고자 Optical Gate구조를 제안하여 이 optically Gated Semiconductor Switching 소자의 동작특성을 연구하고 Injection Gate 구조를 제안하여 이 optically Gated Semiconductor Switching 소자의 동작특성을 연구하고 Injection Gate 및 MOS Gate 구조(Planar type, V-Groove type, Injection Gate mode, Optical Gate mode)로 설계제작된 소자와 특성을 비교 분석하였다.

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Analytic Threshold Voltage Model of Recessed Channel MOSFETs

  • Kwon, Yong-Min;Kang, Yeon-Sung;Lee, Sang-Hoon;Park, Byung-Gook;Shin, Hyung-Cheol
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.10 no.1
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    • pp.61-65
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    • 2010
  • Threshold voltage is one of the most important factors in a device modeling. In this paper, analytical method to calculate threshold voltage for recessed channel (RC) MOSFETs is studied. If we know the fundamental parameter of device, such as radius, oxide thickness and doping concentration, threshold voltage can be obtained easily by using this model. The model predicts the threshold voltage which is the result of 2D numerical device simulation.