A Study on Improvement and Degradation of Si/SiO2 Interface Property for Gate Oxide with TiN Metal Gate |
Lee, Byung-Hyun
(Advanced Technology Development Team 1, Semiconductor R&D Division, Samsung Electronics, Co. Ltd., School of Information and Communication Engineering, Sungkyunkwan University)
Kim, Yong-Il (Advanced Technology Development Team 1, Semiconductor R&D Division, Samsung Electronics, Co. Ltd.) Kim, Bong-Soo (Advanced Technology Development Team 1, Semiconductor R&D Division, Samsung Electronics, Co. Ltd.) Woo, Dong-Soo (Advanced Technology Development Team 1, Semiconductor R&D Division, Samsung Electronics, Co. Ltd.) Park, Yong-Jik (Advanced Technology Development Team 1, Semiconductor R&D Division, Samsung Electronics, Co. Ltd.) Park, Dong-Gun (Advanced Technology Development Team 1, Semiconductor R&D Division, Samsung Electronics, Co. Ltd.) Lee, Si-Hyung (Process Development Team, Semiconductor R&D Division, Samsung Electronics, Co. Ltd.) Rho, Yong-Han (School of Information and Communication Engineering, Sungkyunkwan University) |
1 | B. Maiti, P. J. Tobin, C. Hobbs, R. I. Hegde, F. Huang, D. L. O'Meara, D. Jovanovic, M. Mendicino, J. Chen, D. Connelly, O. Adetutu, J. Mogab, J. Candelaria, and L. B. La, "PVD TiN metal gate MOSFETs on bulk silicon and fully depleted silicon-on-insulator (FDSOI) substrates for deep sub-quarter micron CMOS technology", Electron Devices Meeting, 1998. IEDM '98 Technical Digest., International 6-9, p. 781, 1998 |
2 | D. G. Park and T. K. Kim, "Effects of fluorine and chlorine on the gate oxide integrity of metal-oxide-semiconductor structure", Thin Solid Films, Vol. 483, p. 232, 2005 DOI ScienceOn |
3 | J. C. Hu, H. Yang, R. Kraft, A. L. P. Rotondaro, S. Hattangady, W. W. Lee, R. A. Chapman, C.-P. Chao, A. Chatterjee, M. Hanratty, M. Rodder, and I.-C. Chen, "Feasibility of using W/TiN as metal gate for conventional 0.13 CMOS technology and beyond", Electron Devices Meeting, 1997. Technical Digest., International, p. 825, 1997 |
4 | S. H. Bae, S.-C. Song, K. S. Choi, G. Bersuker, G. A. Brown, D.-L. Kwong, and B. H. Lee, "Thickness optimization of the TiN metal gate with polysilicon-capping layer on Hf-based high-k dielectric", Microelectronic Engineering, Vol. 83, p. 460, 2006 DOI ScienceOn |
5 | S. H. Hong, T. S. Jeon, B. Y. Koo, S. J. Hyun, Y. G. Shin, U.-I. Chung, and J. T. Moon, "The development of dual gate poly scheme with plasma nitrided gate oxide for mobile high performance DRAMs: plasma process monitoring and the correlation with electrical results", Integrated Circuit Design and Technology, ICICDT '04. International Conference on 2004, p. 219, 2004 |
6 | T. S. Jang, M. H. Ha, K. D. Yoo, and B. K. Kang, "Plasma process induced damages on n-MOSFET with plasma oxidized and nitrided gate dielectrics", Microelectronic Engineering, Vol. 75, p. 443, 2004 DOI ScienceOn |
7 | S. Abermann, J. Efavi, G. Sjöblom, M. Lemme, J. Olsson, and E. Bertagnolli, "Impact of Al-, Ni-, TiN-, and Mo-metal gates on MOCVD-grown and dielectrics", Microelectronics Reliability, Vol. 47, p. 536, 2007 DOI ScienceOn |
8 | R. Li and Q. Xu, "Damascene W/TiN gate MOSFETs with improved performance for 0.1-/spl mu/m regime", Electron Devices, IEEE Transactions on, Vol. 49, p. 1891, 2002 DOI ScienceOn |
9 | J. M. Lee, H. S. Seo, and S. N. Hong, "Analysis of PMOS capacitor with thermally robust molybdenium gate", J. of KIEEME(in Korean), Vol. 18, No. 7, p. 594, 2005 과학기술학회마을 DOI ScienceOn |
10 | M. C. Lemme, J. K. Efavi, H. D. B. Gottlob, T. Mollenhauer, T. Wahlbrink, and H. Kurz, "Comparison of metal gate electrodes on MOCVD ", Microelectronics and Reliability, Vol. 45, p. 953, 2005 DOI ScienceOn |
11 | S. S. Tan, C. H. Ang, C. M. Lek, T. P. Chen, B. J. Cho, A. See, and L. Chan, "Characterization of ultrathin plasma nitrided gate dielectrics in pMOSFET for 0.18 um technology and beyond", Physical and Failure Analysis of Integrated Circuits, Proceedings of the 9th International Symposium, p. 254, 2002 |
12 | H. Moriceau, A. M. Cartier, and B. Aspar, "Hydrogen annealing treatment used to obtain high quality SOI surfaces", Proceedings 1998 IEEE International SOI Conference, p. 37, 1998 |
13 | D. H. LEE, S. H. Joo, G. H. Lee, J. Moon, T. E. Shim, and J. G. Lee, "Characteristics of CMOSFETs with sputter-deposited W/TiN stack gate", VLSI Technology, 1995. Digest of Technical Papers. 1995 Symposium on, p. 119, 1995 |
14 | V. Nathan and N. C. Das, "Gate-induced drain leakage current in MOS device", Electron Device, IEEE transactions on, Vol. 40, p. 1888, 1993 DOI ScienceOn |
15 | D. C. Mayer, "Modes of operation and radiation sensitivity of ultra thin SOI transistors", SOS/SOI Technology Conference, p. 52, 1989 |
16 | S. T. Pantelides, S. N. Rashkeev, R. Buczko, D. M. Fleetwood, and R. D. Schrimpf, "Reactions of hydrogen with interfaces", Nuclear Science, IEEE transactions on, Vol. 47, p. 2262, 2000 DOI ScienceOn |
17 | D. J. Dimaria, "Defect production, degradation, and breakdown of silicon dioxide films", Solid-State Electronics, Vol. 41, p. 957, 1997 DOI ScienceOn |
18 | P. K. Hurley, K. Cherkaoui, S. McDonnell, G. Hughes, and A. W. Groenland, "Characterisation and passivation of interface defects in (1 0 0)- gate stacks", Microelectronics Reliability, Vol. 47, p. 1195, 2007 DOI ScienceOn |
19 | H. Kuribayashi, M. Gotoh, R. Hiruta, R. Shimizu, K. Sudoh, and H. Iwasaki, "Observation of Si(1 0 0) surfaces annealed in hydrogen gas ambient by scanning tunneling microscopy", Applied Surface Science, Vol. 252, p. 5275, 2006 DOI ScienceOn |
20 | H. C. Cheng, W. K. Lai, C. C. Hwang, M. H. Juang, S. C. Chu, and T. F. Liu, "Suppression for boron penetration for P+ stacked poly-Si gate by using inductively coupled plasma treatment", IEEE Electron Device Letter, Vol. 20, p. 535, 1999 DOI ScienceOn |
21 | M.C. Lemme, J. K. Efavi, T. Mollenhauer, M. Schmidt, H. D. B. Gottlob, T. Wahlbrink, and H. Kurz, "Nanoscale TiN metal gate technology for CMOS integration", Microelectronic Engineering, Vol. 83, p. 1551, 2006 DOI ScienceOn |
22 | A. Bravaix, D. Vuillaume, D. Goguenheim, D. Dorval, and M. Haond, "Improved hot-carrier immunity of p-MOSFET's with 8nm thick nitrided gate-oxide during bi-directional stressing", Microelectronic Engineering, Vol. 28, p. 273, 1995 DOI ScienceOn |