• Title/Summary/Keyword: Output Matching Circuit

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A General Design Method for the Broadband Multi-Section Power Divider (광대역 다단 전력 분배기의 일반화된 설계 방법)

  • Park, Jun-Seok;Kim, Hyeong-Seok;Im, Jae-Bong
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.51 no.2
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    • pp.85-91
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    • 2002
  • A novel multi-section power divider configuration is Proposed to obtain wide-band frequency performance up to microwave frequency region. Design procedures for the proposed microwave broadband power divider are composed of a Planar multi-section three-Ports hybrid and a waveguide transformer design procedures. The multi∼section power divider is based on design theory of the optimum quarter- wave transformer Furthermore, in order to obtain the broadband isolation performance between the two adjacent output ports, the odd mode equivalent circuit should be matched by using the lossy element such as resistor. The derived design formula for calculating these odd mode∼matching elements is based on the singly terminated filter design theory. The waveguide transformer section is designed to suppress the propagation of the higher order modes such as waveguide modes due to employing the metallic electric wall. Simulation and experiment show excellent performance of multi section power divider.

Development of an Automatic Blood Pressure Device based on Korotkoff Sounds

  • Li, Xiong;Im, Jae Joong
    • International journal of advanced smart convergence
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    • v.8 no.2
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    • pp.227-236
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    • 2019
  • In this study, we develop a Korotkoff sound based automatic blood pressure measurement device including sensor, hardware, and analysis algorithm. PVDF-based sensor pattern was developed to function as a vibration sensor to detect of Korotkoff sounds, and the film's output was connected to an impedance-matching circuit. An algorithm for determining starting and ending points of the Korotkoff sounds was established, and clinical data from subjects were acquired and analyzed to find the relationship between the values obtained by the auscultatory method and from the developed device. The results from 86 out of 90 systolic measurements and 84 out of 90 diastolic measurements indicate that the developed device pass the validation criteria of the international protocol. Correlation coefficients for the values obtained by the auscultatory method and from the developed device were 0.982 and 0.980 for systolic and diastolic blood pressure, respectively. Blood pressure measurements based on Korotkoff sound signals obtained by using the developed PVDF film-based sensor module are accurate and highly correlated with measurements obtained by the traditional auscultatory method.

High Efficiency GaN HEMT Power Amplifier Using Harmonic Matching Technique (고조파 정합 기법을 이용한 고효율 GaN HEMT 전력 증폭기)

  • Jin, Tae-Hoon;Kwon, Tae-Yeop;Jeong, Jinho
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.25 no.1
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    • pp.53-61
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    • 2014
  • In this paper, we present the design, fabrication and measurement of high efficiency GaN HEMT power amplifier using harmonic matching technique. In order to achieve high efficiency, harmonic load-pull simulation is performed, that is, the optimum load impedances are determined at $2^{nd}$ and $3^{rd}$ harmonic frequencies as well as at the fundamental. Then, the output matching circuit is designed based on harmonic load-pull simulation. The measurement of the fabricated power amplifier shows the linear gain of 20 dB and $P_{1dB}$(1 dB gain compression point) of 33.7 dBm at 1.85 GHz. The maximum power added efficiency(PAE) of 80.9 % is achieved at the output power of 38.6 dBm, which belongs to best efficiency performance among the reported high efficiency power amplifiers. For W-CDMA input signal, the power amplifier shows a PAE of 27.8 % at the average output power of 28.4 dBm, where an ACLR (Adjacent Channel Leakage Ratio) is measured to be -38.8 dBc. Digital predistortion using polynomial fitting was implemented to linearize the power amplifiers, which allowed about 6.2 dB improvement of an ACLR performance.

A Highly Linear and Efficient DMB CMOS Power Amplifier with Adaptive Bias Control and 2nd Harmonic Termination circuit (적응형 바이어스 조절 회로와 2차 고조파 종단 회로를 이용한 고선형성 고효율 DMB CMOS 전력증폭기)

  • Choi, Jae-Won;Seo, Chul-Hun
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.44 no.1
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    • pp.32-37
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    • 2007
  • A DMB CMOS power amplifier (PA) with high efficiency and linearity is present. For this work, a 0.13-um standard CMOS process is employed and all components of the proposed PA are fully integrated into one chop including output matching network and adaptive bias control circuit. To improve the efficiency and linearity simultaneously, an adaptive bias control circuit is adopted along with second harmonic termination circuit at the drain node. The PA is shown a $P_{1dB}$ of 16.64 dBm, power added efficiency (PAE) of 38.31 %, and power gain of 24.64 dB, respectively. The third-order intermodulation (IMD3) and the fifth-order intermodulation (IMD5) have been -24.122 dBc and -37.156 dBc, respectively.

Linear Tapered Slot Rectifying Antenna for Portable UHF-Band RFID System (휴대용 UHF대역 RFID 시스템을 위한 선형 테이퍼드 슬롯 정류 안테나)

  • Pyo, Seongmin
    • Journal of IKEEE
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    • v.24 no.1
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    • pp.368-371
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    • 2020
  • In this paper, we propose a linear tapered slot rectifying antenna for a portable UHF-band RFID system. Since the proposed rectifying antenna does not use a dielectric substrate, the planar antenna is implemented with a thin metal thickness. The rectifier circuit converts input RF power into output DC voltage using a voltage doubler circuit based on two anti-parallel schottky diodes. The rectifying antenna is integrated by the voltage doubler circuit into a linear tapered slot antenna. For conjugate impedance matching of the rectifying circuit and the linear tapered slot antenna, the source-pull method was utilized by adjusting the angle of the tapered slot and the length of the antenna feed line. The proposed antenna prototype has been verified with the electrical and radiation characteristics through RF-DC conversion and far-field radiation test in open space measurement environment. Finally, the proposed antenna is realized to 0.23-wavelength (75 mm) and 0.18-wavelength (60 mm) at 915 MHz center frequency.

Design & Fabrication of an InGaP/GaAs HBT MMIC Power Amplifier for IMT-2000 Handsets (IMT-2000 단말기용 InGaP/GaAs HBT MMIC 전력증폭기 설계 및 제작)

  • 채규성;김성일;이경호;김창우
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.28 no.11A
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    • pp.902-911
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    • 2003
  • Using InGaP/GaAs HBT power cells with a 2.0${\times}$20$\mu\textrm{m}$$^2$ emitter area of a unit HBT, a two stage MMIC power amplifier has been developed for IMT-2000 handsets. An active-bias circuit has been used for temperature compensation and reduction in the idling current. Fitting on measured S-parameters of the HBT cells, circuit elements of HBT's nonlinear equivalent model have been extracted. The matching circuits have been designed basically with the extracted model. A two stage HBT MMIC power amplifier fabricated using ETRI's HBT process. The power amplifier produces an 1-㏈ compressed output power(P$\_$l-㏈/) of 28.4 ㏈m with 31% power added efficiency(PAE) and 23-㏈ power gain at 1.95 GHz in on-wafer measurement. Also, the power amplifier produces a 26 ㏈m output power, 28% PAE and a 22.3-㏈ power gain with a -40 ㏈c ACPR at a 3.84 ㎒ off-center frequency in COB measurement.quency in COB measurement.

Characteristics Analysis of Class E Frequency Multiplier using FET Switch Model (FET 스위치 모델을 이용한 E급 주파수 체배기 특성 해석)

  • Joo, Jae-Hyun;Koo, Kyung-Heon
    • Journal of Advanced Navigation Technology
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    • v.15 no.4
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    • pp.596-601
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    • 2011
  • This paper has presented research results for the switching mode class E frequency multiplier that has simple circuit structure and high efficiency. Frequency multiplication is coming from the nonlinearity of the active component, and this paper models the FET active component as a simple switch and some parasitics to analyze the characteristics. The matching component parameters for the class E frequency doubler have been derived with modeling the FET as a input controlled switch and some parasitics. A circuit simulator, ADS, is used to simulate the output voltage and current waveform and efficiency with the variation of the parasitic values. With 2.9GHz input and 2V bias, the drain efficiency has been decreased from 98% to 28% with changing the parasitic capacitance from 0pF to 1pF at 5.8GHz output, which shows that the parasitic capacitance CP has the most significant effect on the efficiency among the parasitics of FET.

On a Modified Structure of Taper Type Planar Power Divider/Combiner at 2 GHz (2 GHz 평면 테이퍼형 전력 분배/결합회로의 수정된 구조 연구)

  • 한용인;김인석
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.13 no.10
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    • pp.1005-1016
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    • 2002
  • In this paper, a 2 GHz tapered shape of multiport power divider/combiner modified from the model published by [10] and adopted PBG(Photonic Band Gap) structure is proposed. Parameters determining electrical property of the circuit structure have been analyzed by HFSS simulation. For input matching, balance of output signals and phase linearity at each output port, one circular hole has been etched out on the circuit surface. 1:2 and 1:3 power dividers/combiners designed by this study have been compared with the same circuits designed by the method of [10] in terms of S-parameters. As a result, it has been found that tile modified structure and PBG of power divider/combiner have improved return loss more than 20 dB and another 18 dB. respectively, at 2 GHz.

Design of Two-Stage Fully-Integrated CMOS Power Amplifier for V-Band Applications (V-대역을 위한 완전 집적된 CMOS 이단 전력증폭기 집적회로 설계)

  • Kim, Hyunjun;Cho, Sooho;Oh, Sungjae;Lim, Wonseob;Kim, Jihoon;Yang, Youngoo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.27 no.12
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    • pp.1069-1074
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    • 2016
  • This paper presents a V-band two-stage power amplifier integrated circuit using TSMC 65 nm CMOS process. The simple input, output, and inter-stage matching networks based on passive components are integrated. By compensating for power gain characteristics using a pre-distortion technique, the linearity of the power amplifier was improved. The implemented two-stage power amplifier showed a power gain of 10.4 dB, a saturated output power of 9.7 dBm, and an efficiency of 20.8 % with a supply voltage of 1 V at the frequency band of 58.8 GHz.

Design and Implementation of QPSK Receiver Using Six-Port Direct Conversion (Six-Port 직접 변환을 이용한 QPSK 수신기 설계 및 제작)

  • Yang, Woo-Jin;Kim, Young-Wan
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.18 no.1 s.116
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    • pp.15-23
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    • 2007
  • A simple six-port direct conversion QPSK receiver which is made up of a six-port phase correlator, a signal power detector, and I/Q channel signal de-modulator is designed and implemented in this paper. The output phase signals of six-port phase correlator are also analysed. On the basis of $90^{\circ}C$ phase relation among the six-port phase correlator output signals, the QPSK de-modulation circuit is designed by a simple circuit. The six-port phase correlator is made up of $90^{\circ}$ hybrid branch line and power detector. The six-port phase correlator, which is designed in frequency range of 11.7 to 12.0 GHz, gets the phase error characteristics less than $5^{\circ}$. By considering matching network and amplitude balance in the designed fiequency range, the designed six-port direct conversion QPSK receiver demodulates the I and Q signals with performance less than $5^{\circ}$ phase error.