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http://dx.doi.org/10.5515/KJKIEES.2016.27.12.1069

Design of Two-Stage Fully-Integrated CMOS Power Amplifier for V-Band Applications  

Kim, Hyunjun (School of Information and Communication Engineering, Sungkyunkwan University)
Cho, Sooho (Hanwha Systems Co., Ltd.)
Oh, Sungjae (School of Information and Communication Engineering, Sungkyunkwan University)
Lim, Wonseob (School of Information and Communication Engineering, Sungkyunkwan University)
Kim, Jihoon (Samsung Electronics Co., Ltd.)
Yang, Youngoo (School of Information and Communication Engineering, Sungkyunkwan University)
Publication Information
Abstract
This paper presents a V-band two-stage power amplifier integrated circuit using TSMC 65 nm CMOS process. The simple input, output, and inter-stage matching networks based on passive components are integrated. By compensating for power gain characteristics using a pre-distortion technique, the linearity of the power amplifier was improved. The implemented two-stage power amplifier showed a power gain of 10.4 dB, a saturated output power of 9.7 dBm, and an efficiency of 20.8 % with a supply voltage of 1 V at the frequency band of 58.8 GHz.
Keywords
Power Amplifier Integrated Circuit; CMOS Power Amplifier; V-Band; Mm-Wave; Pre-Distortionl;
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1 N. Kurita, H. Kondoh, "60 GHz and 80 GHz wide band power amplifier MMICs in 90 nm CMOS technology", IEEE Radio Frequency Integrated Circuits Symp., pp. 39-42. Jun. 2009.
2 A. Siligaris et al., "A 60 GHz power amplifier with 14.5 dBm saturation power and 25 % peak PAE in CMOS 65nm SOI", Proc. of IEEE ESSCIRC, pp. 168-171, Sep. 2009.
3 J. C. Wu, J. C. Kao, J. J. Kuo, K. Y. Kao, and K. Y. Lin, "A 60-GHz single-ended-to-differential vector sum phase shifter in CMOS for phased-array receiver", in IEEE MTT-S Int. Microw. Symp. Dig., pp. 1-4, Jun. 2011.
4 H. Asada, K. Matsushita, K. Bunsen, K. Okada and A. Matsuzawa, "A 60 GHz CMOS power amplifier using capacitive cross-coupling neutralization with 16 % PAE", in European Microw. Conf. 2011, pp. 554-557, Oct. 2011.
5 J. Y. C. Liu, R. Berenguer, and M. C. F. Chang, "Millimeter-wave self-healing power amplifier with adaptive amplitude and phase linearization in 65-nm CMOS", in IEEE Trans. on Micro. Theory Techn., vol. 60, no. 5, pp. 1342-1352, May 2012.   DOI
6 W. Fei, H. Yu, Yuan Liang, and W. M. Lim, "A 54 to 62.8 GHz PA with 95.2 $mW/mm^2$ output power density by $4{\times}4$ distributed in-phase power combining in 65nm CMOS", in IEEE MTT-S Int. Micro. Symp. 2014., pp. 1-4, Jun. 2014.
7 He, Ying, et al. "Design considerations for 60 GHz CMOS power amplifiers", Proc. Asia-Pacific Micro. Conf. 2010., pp. 1613-1616, Dec. 2010.
8 D. Chowdhury, P. Reynaert, and A. M. Niknejad, "Design considerations for 60 GHz transformer-coupled CMOS power amplifiers", in IEEE J. Solid-State Circuits, vol. 44, no. 10, pp. 2733-2744, Oct. 2009.   DOI
9 K. Y. Kao, Y. C. Hsu, K. W. Chen, and K. Y. Lin, "Phase-delay cold-fet pre-distortion linearizer for millimeter-wave CMOS power amplifiers", in IEEE Trans. on Micro. Theory Techn., vol. 61, no. 12, pp. 4505-4519, Dec. 2013.   DOI
10 J. H. Tsai, C. H. Wu, H. Y. Yang, and T. W. Huang, "A 60 GHz CMOS power amplifier with built-in predistortion linearizer", in IEEE Microw. Wireless Compon. Lett., vol. 21, no. 12, pp. 676-678, Dec. 2011.   DOI
11 Y. C. Hsu, K. Y. Kao, J. C. Kao, T. C. Tsai, and K. Y. Lin, "A 60 GHz CMOS power amplifier with modified pre-distortion linearizer", in Proc. IEEE MTT-S Int. Microw. Symp. Dig., pp. 1-4, Jun. 2013.
12 J. Y. C. Liu, Q. J. Gu, A. Tang, N. Y. Wang, and M. C. F. Chang, "A 60 GHz tunable output profile power amplifier in 65 nm CMOS", in IEEE Microw. Wireless Compon. Lett., vol. 21, no. 7, pp. 377-379, Jul. 2011.   DOI