• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.22-29
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• 2007

A 2.5Gb/s 2:1 multiplexer(MUX) IC using $0.18{\mu}m$ CMOS was designed and fabricated. Inductive peaking technology was used to improve the performance. On-chip micro spiral inductor was designed to maximize the inductive peaking effect without increasing the chip area much. The designed 4.7 nH micro-spiral inductor was $20\times20{\mu}m2$ in size. 2:1 MUX with and without micro spiral inductors were compared. The rise and fall time was improved more than 23% and 3% respectively using the micro spiral inductors for 1.25Gb/s signal. For 2.5 Gb/s signal, fall and rise time was improved 5.3% and 3.5% respectively. It consumed 61mW and voltage output swing was 1$180mV_{p-p}$ at 2.5Gb/s.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.8-15
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• 2002

We optimally designed the VCO(voltage-controlled oscillator) with spiral inductor using the MOSIS HP 0.5${\mu}{\textrm}{m}$ CMOS process. With the developed SPICE model of spiral inductor, the quality factor of spiral inductor was maximized at the operating frequency by varying the layout parameters, e.g., metal width, number of turns, radius, space of the metal lines. For the operation frequency of 2㎓, the inductance of about 3nH, and the MOSIS HP 0.5 CMOS process with the metal thickness of 0.8${\mu}{\textrm}{m}$, oxide thickness of 3${\mu}{\textrm}{m}$, the optimal width of metal lines is about 20${\mu}{\textrm}{m}$ for the maximum Quality factor. With the optimized spiral inductor, the VCO with LC tuning tank was designed, fabricated and measured. The measurements were peformed on-wafer using the HP8593E spectrum analyzer. The oscillation frequency was about 1.610Hz, the frequency variation of 250MHz(15%) with control voltage of 0V - 2V, and the phase noise of -108.4㏈c(@600KHz) from output spectrum.

• ETRI Journal
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• v.21 no.4
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• pp.1-8
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• 1999

Thick metal 0.8${\mu}m$ CMOS technology on high resistivity substrate(RF CMOS technology) is demonstrated for the L-band RF IC applications, and we successfully implemented it to the monolithic 900 MHz and 1.9 GHz CMOS LNAs for the first time. To enhance the performance of the RF circuits, MOSFET layout was optimized for high frequency operation and inductor quality was improved by modifying the technology. The fabricated 1.9 GHz LNA shows a gain of 15.2 dB and a NF of 2.8 dB at DC consumption current of 15mA that is an excellent noise performance compared with the offchip matched 1.9 GHz CMOS LNAs. The 900 MHz LNA shows a high gain of 19 dB and NF of 3.2 dB despite of the performance degradation due to the integrating of a 26 nH inductor for input match. The proposed RF CMOS technology is a compatibel process for analog CMOS ICs, and the monolithic LNAs employing the technology show a good and uniform RF performance in a five inch wafer.

• ETRI Journal
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• v.25 no.2
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• pp.65-72
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• 2003

To achieve cost and size reductions, we developed a low cost manufacturing technology for RF substrates and a high performance passive process technology for RF integrated passive devices (IPDs). The fabricated substrate is a conventional 6" Si wafer with a 25${\mu}m$ thick $SiO_2$ surface. This substrate showed a very good insertion loss of 0.03 dB/mm at 4 GHz, including the conductive metal loss, with a 50 ${\Omega}$ coplanar transmission line (W=50${\mu}m$, G=20${\mu}m$). Using benzo cyclo butene (BCB) interlayers and a 10 ${\mu}m$ Cu plating process, we made high Q rectangular and circular spiral inductors on Si that had record maximum quality factors of more than 100. The fabricated inductor library showed a maximum quality factor range of 30-120, depending on geometrical parameters and inductance values of 0.35-35 nH. We also fabricated small RF IPDs on a thick oxide Si substrate for use in handheld phone applications, such as antenna switch modules or front end modules, and high-speed wireless LAN applications. The chip sizes of the wafer-level-packaged RF IPDs and wire-bondable RF IPDs were 1.0-1.5$mm^2$ and 0.8-1.0$mm^2$, respectively. They showed very good insertion loss and RF performances. These substrate and passive process technologies will be widely utilized in hand-held RF modules and systems requiring low cost solutions and strict volumetric efficiencies.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.20 no.5
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• pp.216-220
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• 2010

Ni-Fe alloys have various applications such as thin film inductor, thin film transformer, magnetic head's shield case, etc. Magnetic properties of Ni-Fe thin films depend on the process parameters such as thickness, contents, deposition rate, substrates, etc. In this study, NiFe films with a thickness of about 150nm were deposited on Si(100) wafer and $SiO_2$/Si(100) substrate at room temperature by a DC magnetron co-sputtering using Fe and Ni targets. Their phase formation and magnetic properties as a function of annealing temperature were investigated with XRD, FE-SEM and VSM. The assputtered films have BCC structure. With increasing annealing temperature, NiFe thin film for $SiO_2$/Si(100) substrate transformed completely from BCC to FCC phase above $500^{\circ}C$, but some BCC phase remained above $500^{\circ}C$ on Si(100) wafer. For samples annealed at $450^{\circ}C$, squareness ratio of NiFe thin film shows peak value and its saturation magnetization is around 0.0118 emu, which means that the optimum annealing temperature of NiFe thin film seems to be $450^{\circ}C$. The saturation magnetization of films decreased rapidly above the annealing temperature of $500^{\circ}C$ due to phase transformation from BCC to FCC phase.

• Journal of information and communication convergence engineering
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• v.4 no.4
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• pp.155-157
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• 2006

This paper presents the thermal technique to improve characteristic of planar spiral inductors. The spiral inductors were fabricated on silicon dioxide/silicon (SiO2/Si) wafer. The thermal treatment was done by annealing processes. The measure results showed a considerable improvement of return loss (Sl1). This thermal treatment seems very promising for enhancing spiral inductors based RF IC's.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.3
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• pp.1-6
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• 2017

As the performance and density of IC devices increase, especially the clock frequency increases, power grid network integrity problems become more challenging. To resolve these power integrity problems, the use of passive devices such as resistor, inductor, and capacitor is very important. To manage the power integrity with little noise or ripple, decoupling capacitors are essential in electronic packaging. The decoupling capacitors are classified into voltage regulator capacitor, board capacitor, package capacitor, and on-chip capacitor. For next generation packaging technologies such as 3D packaging or wafer level packaging on-chip MIM decoupling capacitor is the key element for power distribution and delivery management. This paper reviews the use and necessity of on-chip decoupling capacitor.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.10 s.101
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• pp.989-994
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• 2005

A MMIC(Monolithic Microwave Integrated Circuit) switch chip using InGaAs/GaAs p-HEMT process has been designed for MSM(Microwave Switch Matrix) of satellite communication system. An absorptive type MMIC switch is adopted for good reflection coefficients performances of input and output ports at both on and off states. And, a quarter wavelength impedance transformer is realized with lumped elements of MIM capacitor and spiral inductor for 3 GHz band to reduce the chip size. This MMIC switch covers the frequency range of $3.2\~3.6\;GHz$. According to the on-wafer measurement, the fabricated MMIC switch with miniature size of $1.6\;mm{\times}1.3\;mm$ demonstrates insertion loss below 2 dB and isolation above 56.8 dB, and the performance coincides with simulation results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.5
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• pp.1023-1028
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• 2012

A MMIC (Monolithic Microwave Integrated Circuit) mixer chip using the Schottky diode of an GaAs p-HEMT process has been developed for the I/Q demodulator of non-contact near field microwave probing system. A single balanced mixer type is adopted to achieve simple structure of the I/Q demodulator. A quadrature hybrid coupler and a quarter wavelength transmission line for 180 degree hybrid are realized with lumped elements of MIM capacitor and spiral inductor to reduce the mixer chip size. According to the on-wafer measurement, this MMIC mixer covers RF and LO frequencies of 1650MHz to 2050MHz with flat conversion loss. The MMIC mixer with miniature size of $2.5mm{\times}1.7mm$ demonstrates conversion loss below 12dB for both variations of RF and LO frequencies, LO-to-IF isolation above 43dB and RF-to-IF isolation above 23dB, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.11a
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• pp.291-294
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• 1996

We present the experimental results of high quality factor (Q) inductors fabricated on high-resistivity silicon wafer using standard CMOS process without any modificatons such as thick gold layer or multilayer interconnection. This demonstrates the possibility of building high Q inductors using lower cost technologies, compared with previous results using complicated process. The comparative analysis is carried out to find the optimized inductor shape for the maximum performance by varying the thickness of metal and number of turns with rectangular shape.