• Title/Summary/Keyword: On-chip bus

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Design of Crossbar Switch On-chip Bus for Performance Improvement of SoC (SoC의 성능 향상을 위한 크로스바 스위치 온칩 버스 설계)

  • Heo, Jung-Burn;Ryoo, Kwang-Ki
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.3
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    • pp.684-690
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    • 2010
  • Most of the existing SoCs have shared bus architecture which always has a bottleneck state. The more IPs are in an SOC, the less performance it is of the SOC, Therefore, its performance is effected by the entire communication rather than CPU speed. In this paper, we propose cross-bar switch bus architecture for the reduction of the bottleneck state and the improvement of the performance. The cross-bar switch bus supports up to 8 masters and 16 slaves and parallel communication with architecture of multiple channel bus. Each slave has an arbiter which stores priority information about masters. So, it prevents only one master occupying one slave and supports efficient communication. We compared WISHBONE on-chip shared bus architecture with crossbar switch bus architecture of the SOC platform, which consists of an OpenRISC processor, a VGA/LCD controller, an AC97 controller, a debug interface, a memory interface, and the performance improved by 26.58% than the previous shared bus.

A Bus Data Compression Method for High Resolution Mobile Multimedia SoC (고해상 모바일 멀티미디어 SoC를 위한 온칩 버스 데이터 압축 방법)

  • Lee, Jin;Lee, Jaesung
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2013.05a
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    • pp.345-348
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    • 2013
  • This paper provides a method for compression and transmission of on-chip bus data. As the data traffic on on-chip buses is rapidly increasing with enlarged video resolutions, many video processor chips suffer from a lack of bus bandwidth and their IP cores have to wait for a longer time to get a bus grant. In multimedia data such as images and video, the adjacent data signals very often have little or no difference between them. Taking advantage of this point, this paper develops a simple bus data compression method to improve the chip performance and presents its hardware implementation. The method is applied to a Video Codec - 1 (VC-1) decoder chip and reduces the processing time of one macro-block by 13.6% and 10.3% for SD and HD videos, respectively.

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A GA-based Floorplanning method for Topological Constraint

  • Yoshikawa, Masaya;Terai, Hidekazu
    • 제어로봇시스템학회:학술대회논문집
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    • 2005.06a
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    • pp.1098-1100
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    • 2005
  • The floorplanning problem is an essential design step in VLSI layout design and it is how to place rectangular modules as density as possible. And then, as the DSM advances, the VLSI chip becomes more congested even though more metal layers are used for routing. Usually, a VLSI chip includes several buses. As design increases in complexity, bus routing becomes a heavy task. To ease bus routing and avoid unnecessary iterations in physical design, we need to consider bus planning in early floorplanning stage. In this paper, we propose a floorplanning method for topological constraint consisting of bus constraint and memory constraint. The proposed algorithms based on Genetic Algorithm(GA) is adopted a sequence pair. For selection control, new objective functions are introduced for topological constraint. Studies on floor planning and cell placement have been reported as being applications of GA to the LSI layout problem. However, no studies have ever seen the effect of applying GA in consideration of topological constraint. Experimental results show improvement of bus and memory constraint.

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Distributed arbitration scheme for on-chip CDMA bus with dynamic codeword assignment

  • Nikolic, Tatjana R.;Nikolic, Goran S.;Djordjevic, Goran Lj.
    • ETRI Journal
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    • v.43 no.3
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    • pp.471-482
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    • 2021
  • Several code-division multiple access (CDMA)-based interconnect schemes have been recently proposed as alternatives to the conventional time-division multiplexing bus in multicore systems-on-chip. CDMA systems with a dynamic assignment of spreading codewords are particularly attractive because of their potential for higher bandwidth efficiency compared with the systems in which the codewords are statically assigned to processing elements. In this paper, we propose a novel distributed arbitration scheme for dynamic CDMA-bus-based systems, which solves the complexity and scalability issues associated with commonly used centralized arbitration schemes. The proposed arbitration unit is decomposed into multiple simple arbitration elements, which are connected in a ring. The arbitration ring implements a token-passing algorithm, which both resolves destination conflicts and assigns the codewords to processing elements. Simulation results show that the throughput reduction in an optimally configured dynamic CDMA bus due to arbitration-related overheads does not exceed 5%.

SNP: A New On-Chip Communication Protocol for SoC (SNP : 시스템 온 칩을 위한 새로운 통신 프로토콜)

  • Lee Jaesung;Lee Hyuk-Jae;Lee Chanho
    • Journal of KIISE:Computer Systems and Theory
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    • v.32 no.9
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    • pp.465-474
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    • 2005
  • For high density SoC design, on-chip communication based on bus interconnection encounters bandwidth limitation while an NoC(Network-on-Chip) approach suffers from unacceptable complexity in its Implementation. This paper introduces a new on-chip communication protocol, SNP (SoC Network Protocol) to overcome these problems. In SNP, conventional on-chip bus signals are categorized into three groups, control, address, and data and only one set of wires is used to transmit all three groups of signals, resulting in the dramatic decrease of the number of wires. SNP efficiently supports master-master communication as well as master-slave communication with symmetric channels. A sequencing rule of signal groups is defined as a part of SNP specification and a phase-restoration feature is proposed to avoid redundant signals transmitted repeatedly over back-to-back transactions. Simulation results show that SNP provides about the same bandwidth with only $54\%$ of wires when compared with AMBA AHB.

Separated Address/Data Network Design for Bus Protocol compatible Network-on-Chip (버스 프로토콜 호환 가능한 네트워크-온-칩에서의 분리된 주소/데이터 네트워크 설계)

  • Chung, Seungh Ah;Lee, Jae Hoon;Kim, Sang Heon;Lee, Jae Sung;Han, Tae Hee
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.4
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    • pp.68-75
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    • 2016
  • As the number of cores and IPs increase in multiprocessor system-on-chip (MPSoC), network-on-chip (NoC) has emerged as a promising novel interconnection architecture for its parallelism and scalability. However, minimization of the latency in NoC with legacy bus IPs must be addressed. In this paper, we focus on the latency minimization problem in NoC which accommodates legacy bus protocol based IPs considering the trade-offs between hop counts and path collisions. To resolve this problem, we propose separated address/data network for independent address and data phases of bus protocol. Compared to Mesh and irregular topologies generated by TopGen, experimental results show that average latency and execution time are reduced by 19.46% and 10.55%, respectively.

Characteristic comparison of various arbitration policies using TLM method (TLM 방법을 이용한 다양한 중재 방식의 특성 비교)

  • Lee, Kook-Pyo;Koh, Si-Young
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.13 no.8
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    • pp.1653-1658
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    • 2009
  • SoC(System on a Chip) has several masters, slaves, arbiter and decoder in bus architecture. Master initiates the data transactions like CPU, DMA and DSP and slave responses the data transactions like SRAM, SDRAM and register. Furthermore, as multiple masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, SoC performance can be changed definitely. In this study, we compare the characteristics of various arbitration policies using TLM(Transaction Level Model) method. Fixed priority, round-robin, TDMA and Lottery bus policies are used in general arbitration method. We analyze the merit and demerit of these arbitration policies.

The Hybrid Bus arbitration policy (하이브리드 버스 중재 방식)

  • Lee, Kook-Pyo;Yoon, Yung-Sup
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.2
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    • pp.50-56
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    • 2009
  • SoC(System on a Chip) has several masters, slaves, arbiter and decoder in bus architecture. Master initiates the data transactions like CPU, DMA and DSP and slave responses the data transactions like SRAM SDRAM and register. Furthermore, as multiple masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, SoC performance can be changed definitely. Fixed priority, round-robin, TDM arbitration are used in general arbitration method, In this study, we compose TLM algorithm and analyze general arbitration methods through TLM simulation. Consequently, we propose the hybrid bus arbitration policy and verify the performance, compared with the other arbitration methods.

Design and Implementation of e2eECC for Automotive On-Chip Bus Data Integrity (차량용 온칩 버스의 데이터 무결성을 위한 종단간 에러 정정 코드(e2eECC)의 설계 및 구현)

  • Eunbae Gil;Chan Park;Juho Kim;Joonho Chung;Joosock Lee;Seongsoo Lee
    • Journal of IKEEE
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    • v.28 no.1
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    • pp.116-122
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    • 2024
  • AMBA AHB-Lite bus is widely used in on-chip bus protocol for low-power and cost-effective SoC. However, it lacks built-in error detection and correction for end-to-end data integrity. This can lead to data corruption and system instability, particularly in harsh environments like automotive applications. To mitigate this problem, this paper proposes the application of SEC-DED (Single Error Correction-Double Error Detection) to AMBA AHB-Lite bus. It aims not only to detect errors in real-time but also to correct them, thereby enhancing end-to-end data integrity. Simulation results demonstrate real-time error detection and correction when errors occur, which bolsters end-to-end data integrity of automotive on-chip bus.

Extremely large-area travelling-wave dielectrophoresis microbead separator using a multilayered bus bar (다층 버스 바를 이용한 극한 면적의 진행파 유전영동 미세입자 분류기)

  • Choi, Eun-Pyo;Kim, Byung-Kyu;Park, Jung-Yul
    • Journal of Sensor Science and Technology
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    • v.18 no.2
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    • pp.139-146
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    • 2009
  • A Multilayered microelectrode design is presented for large area travelling wave dielectrophoresis (TwDEP) separators. Most of typical TwDEP chip has been arrayed with 1000 electrodes in $20{\times}20\;mm^2$. However, there is a limitation of the device area that is critical in throughput, because when the area of TwDEP becomes larger, the resistance of microelectrodes for bus bar is also increased. In this paper, we successfully developed a novel TwDEP chip with extremely large area ($31{\times}25\;mm^2$) by a unique multilayered bus bar design. According to the resistance simulation of our microelectrodes, it is possible to realize a TwDEP chip with an infinite longitudinal length. We demonstrated the feasibility of our suggestion with latex microbeads and showed the potential of extremely high throughput separation with TwDEP technique.