Browse > Article
http://dx.doi.org/10.6109/JKIICE.2009.13.8.1653

Characteristic comparison of various arbitration policies using TLM method  

Lee, Kook-Pyo (영진전문대학 전자정보통신계열)
Koh, Si-Young (경일대학교 전자정보통신공학부)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.13, no.8, 2009 , pp. 1653-1658 More about this Journal
Abstract
SoC(System on a Chip) has several masters, slaves, arbiter and decoder in bus architecture. Master initiates the data transactions like CPU, DMA and DSP and slave responses the data transactions like SRAM, SDRAM and register. Furthermore, as multiple masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, SoC performance can be changed definitely. In this study, we compare the characteristics of various arbitration policies using TLM(Transaction Level Model) method. Fixed priority, round-robin, TDMA and Lottery bus policies are used in general arbitration method. We analyze the merit and demerit of these arbitration policies.
Keywords
SoC; arbiter; Fixed priority; Round-robin; TDMA; Lottery bus;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
1 AMBA TM Specification(AHB) (Rev 2.0), ARM Ltd, May 1999
2 K. Lahiri, A. Raghunathan and G. Lakshminarayana, "The LOTTERYBUS On-Chip Communication Architecture," IEEE Trans. VLSI Systems, vol.14, no.6, 2006
3 Y. Xu, L. Li, Ming-lun Gao, B. Zhand, Zhao-yu jiand, Gao-ming Du and W.Zhang, "An Adaptive Dynamic Arbiter for Multi-Processor SoC," Solid-State and Integrated Circuit Technology International Conf., pp.1993-1996, 2006
4 E. Salminen, V. Lahtinen, K. Kuusilinna and T. Hamalainen, "Overview of bus-based system-on-chip interconnections," in Proc. IEEE Int.Symp. Circuits Syst., pp.II-372-II-375, 2002
5 A. B. Kovaleski, "High-Speed Bus Arbiter for Multiprocessor," IEEE Proc., Vol. 130, Pr, E, No.2, March 1983
6 이국표, 윤영섭,"마스터와 슬레이브에 따른 싱글버스와 다중버스 토폴로지의 성능분석," 전자공학회논문지, 제45권 SD편 제9호, pp.96-102, 2008
7 K. Lahiri, A. Raghunathan and S. Dey, "Design Space Exploration for Optimizing On-Chip Communication Architectures," IEEE Trans. Computer-Aided Design, vol.23, pp.952.961, June. 2004