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http://dx.doi.org/10.5573/ieie.2016.53.4.068

Separated Address/Data Network Design for Bus Protocol compatible Network-on-Chip  

Chung, Seungh Ah (College of Information & Communication Engineering, Sungkyunkwan University)
Lee, Jae Hoon (College of Information & Communication Engineering, Sungkyunkwan University)
Kim, Sang Heon (College of Information & Communication Engineering, Sungkyunkwan University)
Lee, Jae Sung (College of Information & Communication Engineering, Sungkyunkwan University)
Han, Tae Hee (College of Information & Communication Engineering, Sungkyunkwan University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.53, no.4, 2016 , pp. 68-75 More about this Journal
Abstract
As the number of cores and IPs increase in multiprocessor system-on-chip (MPSoC), network-on-chip (NoC) has emerged as a promising novel interconnection architecture for its parallelism and scalability. However, minimization of the latency in NoC with legacy bus IPs must be addressed. In this paper, we focus on the latency minimization problem in NoC which accommodates legacy bus protocol based IPs considering the trade-offs between hop counts and path collisions. To resolve this problem, we propose separated address/data network for independent address and data phases of bus protocol. Compared to Mesh and irregular topologies generated by TopGen, experimental results show that average latency and execution time are reduced by 19.46% and 10.55%, respectively.
Keywords
NoC; Topology generation; Latency; Contention; Bus protocol;
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