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Electronics and Telecommunications Research Institute (한국전자통신연구원)
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Distributed arbitration scheme for on-chip CDMA bus with dynamic codeword assignment

  • Nikolic, Tatjana R. (Faculty of Electronic Engineering, University of Nis) ;
  • Nikolic, Goran S. (Faculty of Electronic Engineering, University of Nis) ;
  • Djordjevic, Goran Lj. (Faculty of Electronic Engineering, University of Nis)
  • Received : 2020.01.22
  • Accepted : 2020.05.25
  • Published : 2021.06.01
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Abstract

Several code-division multiple access (CDMA)-based interconnect schemes have been recently proposed as alternatives to the conventional time-division multiplexing bus in multicore systems-on-chip. CDMA systems with a dynamic assignment of spreading codewords are particularly attractive because of their potential for higher bandwidth efficiency compared with the systems in which the codewords are statically assigned to processing elements. In this paper, we propose a novel distributed arbitration scheme for dynamic CDMA-bus-based systems, which solves the complexity and scalability issues associated with commonly used centralized arbitration schemes. The proposed arbitration unit is decomposed into multiple simple arbitration elements, which are connected in a ring. The arbitration ring implements a token-passing algorithm, which both resolves destination conflicts and assigns the codewords to processing elements. Simulation results show that the throughput reduction in an optimally configured dynamic CDMA bus due to arbitration-related overheads does not exceed 5%.

Keywords

Acknowledgement

This work was supported by the Ministry of Education, Science and Technological Development of the Republic of Serbia.

References

  1. S. Pasricha and N. Dutt, On-chip communication architectures: System on chip interconnect, Morgan Kaufmann, Burlington, USA, 2008.
  2. A. Karkar et al., A Survey of emerging interconnects for on-chip efficient multicast and broadcast in many-cores, IEEE Circ. Syst. Mag. 16 (2016), 58-72. https://doi.org/10.1109/MCAS.2015.2510199
  3. S. J. Hollis et al., Exploiting emergence in on-chip interconnects, IEEE Trans. Comput. 63 (2014), 570-582. https://doi.org/10.1109/TC.2012.273
  4. J. Kim, I. Verbauwhede, and M.-C. F. Chang, Design of an interconnect architecture and signaling technology for parallelism in communication, IEEE Trans. VLSI Syst. 15 (2007), 881-894. https://doi.org/10.1109/TVLSI.2007.900739
  5. J. Kim et al., A cost-effective latency-aware memory bus for symmetric multiprocessor systems, IEEE Trans. Comput. 57 (2008), 1714-1719. https://doi.org/10.1109/TC.2008.96
  6. A. Assad et al., A survey on energy-efficient methodologies and architectures of network-on-chip, Comput. Elect. Eng. 40 (2014), 333-347. https://doi.org/10.1016/j.compeleceng.2014.07.012
  7. D. Siguenza-Tortosa, T. Ahonen, and J. Nurmi, Issues in the development of a practical NoC: The Proteo concept, Integr. VLSI J. 38 (2004), 95-105. https://doi.org/10.1016/j.vlsi.2004.07.015
  8. D. Sanchez, G. Michelogiannakis, and C. Kozyrakis, An Analysis of on-chip interconnection networks for large-scale chip multiprocessors, ACM Trans. Archit. Code Optimization 7 (2010), 1-28.
  9. R. H. Bell et al., CDMA as a multiprocessor interconnect strategy, in Proc. Conf. record Asilomar Conf Signals, Syst. COmput. (Pacific Grove, CA, USA), Nov. 2001, pp. 1246-1250.
  10. D. Kim, M. Kim, and G. E. Sobelman, CDMA-based network-onchip architecture, in Proc. IEEE Asia-Pacific Conf. Circuits Syst. (Tainan, Taiwan), Dec. 2004, pp. 137-140.
  11. T. Nikolic, M. Stojcev, and G. Djordjevic, CDMA bus-based onchip interconnect infrastructure, Microel. Reliabil. 49 (2009), 448-459. https://doi.org/10.1016/j.microrel.2009.02.002
  12. X. Wang, T. Ahonen, and J. Nurmi, Applying CDMA technique to network-on-chip, IEEE Trans. VLSI Syst. 15 (2007), 1091-1100. https://doi.org/10.1109/TVLSI.2007.903914
  13. J. Wang et al., A new parallel CODEC technique for CDMA NoCs, IEEE Trans. Indust. Elect. 65 (2018), 6527-6537. https://doi.org/10.1109/tie.2017.2786230
  14. K. E. Ahmed, R. Rizkand, and M. M. Farag, Overloaded CDMA crossbar for network on chip, IEEE Trans. VLSI Syst. 25 (2017), 1842-1855. https://doi.org/10.1109/TVLSI.2017.2664660
  15. B. Halak, T. Ma, and X. Wei, A dynamic CDMA network for multicore systems, Microelectron. J. 45 (2014), 424-434. https://doi.org/10.1016/j.mejo.2014.02.002
  16. M. Kim, D. Kim, and G. E. Sobelman, Adaptive scheduling for CDMA-based networks-on-chip, in Proc. Int. IEEE-NEWCAS Conf. (Quebec, Canada), June, 2005, pp. 357-360. https://doi.org/10.1109/NEWCAS.2005.1496682
  17. W. Lee and G. E. Sobelman, Semi-distributed scheduling for flexible codeword assignment in a CDMA network-on-chip, in Proc. IEEE 8th Int. Conf. ASIC (Changsha, China), 2009, pp. 431-434. https://doi.org/10.1109/ASICON.2009.5351263
  18. C. Hamacher et al., Computer Organization and Embedded Systems 6th ed, McGraw-Hill Education, New York, 2012.
  19. M. B. Slimane, I. B. Hafaiedh, and R. Robbana, Formal-based design and verification of SoC arbitration protocols: A comparative analysis of TDMA and Round-Robin, IEEE Des. Test 34 (2017), 54-62.
  20. A. Kulmala, E. Salminen, and T. D. Hamalainen, Distributed bus arbitration algorithm comparison on FPGA-based MPEG-4 multiprocessor system on chip, IET Comput. Digital Techniq. 2 (2008), 314-325. https://doi.org/10.1049/iet-cdt:20070072
  21. J. Nurmi (ed.), Interconnect-Centric Design for Advanced SoC and NoC, Kluwer Academic Publishers, Dordrecht, The Netherlands, 2004.
  22. J. Wang, Z. Lu, and Y. Li, A new CDMA encoding/decoding method for on-chip communication network, IEEE Trans. VLSI Syst. 24 (2016), 1607-1611. https://doi.org/10.1109/TVLSI.2015.2471077
  23. B. Golubov, A. Efimov, and V. Skvortsov, Walsh Series and Transforms: Theory and Applications, Kluwer Academic Publishers, Dordrecht, The Netherlands, 1991.
  24. A. M. Chan et al., Low-Complexity Localized Walsh Decoding for CDMA Systems, in Proc. IEEE Military Comm. Conf. MILCOM (Washington, DC, USA), 2006, pp. 1-6.
  25. T. R. Nikolic et al., Improving fault-tolerance capability of on-chip binary CDMA bus, J. Supercomput. 72 (2016), 275-294. https://doi.org/10.1007/s11227-015-1513-x