• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.25-32
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• 2011

Networks-on-chip (NoC) is emerging as a key technology to overcome severe bus traffics in ever-increasing complexity of the Multiprocessor systems-on-chip (MPSoC); however traditional electrical interconnection based NoC architecture would be faced with technical limits of bandwidth and power consumptions in the near future. In order to cope with these problems, a hybrid optical NoC architecture which use both electrical interconnects and optical interconnects together, has been widely investigated. In the hybrid optical NoCs, wormhole switching and simple deterministic X-Y routing are used for the electrical interconnections which is responsible for the setup of routing path and optical router to transmit optical data through optical interconnects. Optical NoC uses circuit switching method to send payload data by preset paths and routers. However, conventional hybrid optical NoC has a drawback that concurrent transmissions are not allowed. Therefore, performance improvement is limited. In this paper, we propose a new routing algorithm that uses circuit switching and adaptive algorithm for the electrical interconnections to transmit data using multiple paths simultaneously. We also propose an efficient method to prevent livelock problems. Experimental results show up to 60% throughput improvement compared to a hybrid optical NoC and 65% power reduction compared to an electrical NoC.

• ETRI Journal
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• v.28 no.4
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• pp.475-485
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• 2006

Network-on-chip (NoC) is an emerging design paradigm intended to cope with future systems-on-chips (SoCs) containing numerous built-in cores. Since NoCs have some outstanding features regarding design complexity, timing, scalability, power dissipation and so on, widespread interest in this novel paradigm is likely to grow. The test strategy is a significant factor in the practicality and feasibility of NoC-based SoCs. Among the existing test issues for NoC-based SoCs, test access mechanism architecture and test scheduling particularly dominate the overall test performance. In this paper, we propose an efficient NoC-based SoC test scheduling algorithm based on a rectangle packing approach used for current SoC tests. In order to adopt the rectangle packing solution, we designed specific methods and configurations for testing NoC-based SoCs, such as test packet routing, test pattern generation, and absorption. Furthermore, we extended and improved the proposed algorithm using multiple test clocks. Experimental results using some ITC'02 benchmark circuits show that the proposed algorithm can reduce the overall test time by up to 55%, and 20% on average compared with previous works. In addition, the computation time of the algorithm is less than one second in most cases. Consequently, we expect the proposed scheduling algorithm to be a promising and competitive method for testing NoC-based SoCs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.69-78
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• 2010

To implement the high performance SoC, we propose the flying master bus architecture that a specially defined master named as the flying master directly accesses the selected slaves with no regard to the bus protocol. The proposed bus architecture was implemented through Verilog and mapped the design into Hynix 0.18um technology. As master and slave wrappers have around 150 logic gate counts, the area overhead is still small considering the typical area of modules in SoC designs. In TLM performance simulation about proposed architecture, 25~40% of transaction cycle and 43~60% of bus efficiency are increased and 43~77% of request cycle is decreased, compared with conventional bus architecture. Conclusively, we assume that the proposed flying master bus architecture is promising as the leading candidate of the bus architecture in the aspect of performance and efficiency.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.505-513
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• 2017

As mobile systems are performing various functionality in the IoT (Internet of Things) era, network-on-chip (NoC) plays a pivotal role to support communication between the tens and in the future potentially hundreds of interacting modules in system-on-chips (SoCs). Owing to intensive research efforts more than a decade, NoCs are now widely adopted in various SoC designs. Especially, studies on application-specific NoCs (ASNoCs) that consider the heterogeneous nature of modern SoCs contribute a significant share to use of NoCs in actual SoCs, i.e., ASNoC connects non-uniform processing units, memory, and other intellectual properties (IPs) using flexible router positions and communication paths. Although it is not difficult to find the prior works on ASNoC synthesis and optimization, little research has addressed the issues how to convert different protocols and data widths to make a NoC compatible with various IPs. Thus, in this paper, we address important issues on ASNoC implementation to support and convert multiple interfaces. Based on the in-depth discussions, we finally introduce our FPGA-proven full-custom ASNoC.

• Journal of the Korean Institute of Landscape Architecture
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• v.25 no.3
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• pp.186-198
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• 1997

Although Jaesil are historical products which is related to our traditional culture, they have not been studied extensively. This study deals with the location and the spacial compositional characteristics of Jaesil, a traditional building special functions in culture. The summarized results are as follows : 1) Jaesil wee constructed in 15c~20c. Jaesil in Kyungpook province were built by the intelligent classes in 17c~18c, while Jaesil in Kyungnam province were built by the rich farmer classes with economic power in 19c~20c. 2) The functions of Jaesil were the following : It was used for the purpose of worship, school, temple. The main function in Kyungpook province was worship, while the main functions in Kyungnam province were worship and school. 3) The relationship between Jaesil and villages were as follows : Jaesil in Kyungpook were located in the mountains apart from villages and their main elements of landscape were valleys or rivers . While Jaesil in Kyungnam was located in the residental spaces and their main elements of landscape were an artificial pond or no water landscape. 4) The plane form of Jaesil, Which was constructed specially 'The ㅁtype' of Jaesil were common in Kyungpook province and tis type expresses the enclosure and centrifugal force. While 'The 一type and 二type' were common in Kyungnam, and this types expresses the poenness and practicality.

• Journal of the Korean Institute of Landscape Architecture
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• v.23 no.3
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• pp.106-112
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• 1995

This study was conducted to investigate the environmental factors of habitat of Lindera erythrocarpa and to test seedling growth of the plant transplanted in a field of Sung Kyun Kwan Univ. in Suwon, Kyungkido. The results were as follows ; 1. The wild lindera erythrocarpa was growing in Mt. Kwan whose January average temperature was -3.4$^{\circ}C$, and minimum average temperature was -14.8$^{\circ}C$ in January. It was also growing in Mt. Suri whose daily minimum temperature is 3.4$^{\circ}C$ lower than that of Seoul. Therefore, there was no problem for Lindera erythrocarpa to grow in Seoul regions in terms of winter coldness. 2. The growth of seedlings of Lindera erythrocarpa transplanted in a field of Sung Kyun Kwan Univ. in Suwon, Kyunkido in 1990 showed that average height of the tree was 1.64m, average diameter of root was 2.44cm, and that average width of crown was 1m. Therefore, there was no problem for Lindera erythrocarpa to grow under winter coldness in Suwon area.

• IEMEK Journal of Embedded Systems and Applications
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• v.5 no.1
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• pp.1-6
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• 2010

본 논문에서는 네트워크 온 칩(NoC: network on chip) 구조에서의 내부 데이터 통신의 성능을 최적화 할 수 있는 새로운 온 칩 네트워크 인터페이스 구조를 제안하였다. 제안하는 NoC 구조는 기본적으로 하드웨어 면적을 줄이기 위하여 XY 라우팅 알고리듬을 기반으로 구현되었으며, 전달되는 패킷의 크기 또는 플릿의 개수를 최소화하기 위하여 Golomb-Rice 인코딩/디코딩 알고리듬에 기반을 둔 하드웨어 압축기/해제기를 이용하여 통신되는 데이터의 양을 크게 줄임으로써 네트워크 지연시간을 최소화 할 수 있는 새로운 구조를 제안하였다. 즉 전송될 데이터는 전송자(sender)의 네트워크 인터페이스에서 내장된 하드웨어 인코더를 통해 압축된 형태로 패킷의 개수를 최소화하여 온 칩 네트워크상의 데이터를 업로드하게 된다. 이러한 압축된 데이터가 리시버(receiver)에 도착하면, 하드웨어 디코더를 통해서 원래의 데이터로 복원된다. 사이클 수준의 시뮬레이터를 통하여 제안된 라우터 구조가 온 칩 시스템의 네트워크 지연시간을 크게 줄일 수 있음을 증명하였다.

• The KIPS Transactions:PartD
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• v.8D no.6
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• pp.645-656
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• 2001

Recently, component-based development (CBD) is rapidly spreading as a way of improving the reusability, productivity, and quality of software. For CBD to be effective in achieving such design objectives, the creation and integration of components must be based on a well-defined architecture that guides the correct composition and cooperation of application components. Software architecture must be described using an architecture description language (ADL) to ensure the correctness and preciseness of architecture models. In this paper, we propose the system architecture of an ADL tool set that can effectively support the use of CBD based on the domain architecture and we describe each component of the proposed system architecture. We also modify and redefine C2SADL that was developed to support the use of the description of C2 architectural style by UCI (University of California in Irvine) to facilitate the integration of separately described architecture models, and introduce the method of design and implementation of our ADL processor that partially implements the proposed ADL system architecture.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.71-78
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• 2006

An NoC (Networks-on-Chip) is an emerging design paradigm intended to cope with a future SoC containing numerous built-in cores. In an NoC, the test strategy is very significant for its practicality and feasibility. Among existing test issues, TAM architecture and test scheduling will particularly dominate the overall test performance. In this paper, we address an efficient NoC test scheduling algorithm based on a rectangle packing approach used for an SoC test. In order to adopt the rectangle packing solution as an NoC test scheduling algorithm we design the configuration about test resources and test methods suitable for an NoC structure. Experimental results using some ITC'02 benchmark circuits show the proposed algorithm can reduce the overall test time by up to $55\%$ in comparison with previous works.

• Journal of agriculture & life science
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• v.44 no.3
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• pp.23-30
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• 2010

The optimal growth condition of in vitro stem cutting of Dendrobium nobile 'Hamana Lake Dream' ${\times}$ 'No. 55' was investigated. Among various media and their concentrations, MS media had better effect on the growth of micro stem cutting than Hyponex media in all concentration levels except stem length. The activated charcoal concentration in MS media showed different effects on number of stem and root, leaf length, and fresh weight: the most effective in the range of 0.1 to 1.0 g/L and barely effective above 2.0 g/L. Addition of agar 5 g/L, sucrose at 40 g/L, and peptone at 1 g/L to MS media increased significantly stem length, leaf width, and fresh weight, internode length and number of roots, and the number of stem and leaves. On the other hand, addition of gelite with any concentration had no effect on the growth of micro stem cutting compare to that of control. The optimal temperature for growth of micro stem cutting was $28^{\circ}C$. Under the same temperature, MS medium was better than Hyponex medium for the growth of stem. In addition, sucrose at 40 g/L was the most effective on growth at $28^{\circ}C$.