1 |
K. Lahiri, A. Raghunathan, and G. Lakshminarayana, 'The LOTTERYBUS On-Chip Communication Architecture,' IEEE Trans. VLSI Systems, vol.14, no.6, 2006
|
2 |
Y. Xu, L. Li, Ming-lun Gao, B.Zhand, Zhao-yu Jiand, Gao-ming Du, W. Zhang, 'An Adaptive Dynamic Arbiter for Multi-Processor SoC', Solid-State and Integrated Circuit Technology International Conf., pp.1993-1996, 2006
|
3 |
ARM, Limited. AMBA Specification, 1999
|
4 |
Chiung-San Lee, 'High-Fair Bus Arbiter for Multiprocessors,' IEICE Trans. Inf. & Syst., vol.E80-D, no.1, 1997
|
5 |
Sonics, Inc., Mountain View, CA, 'Silicon micronetworks technical overview,' 2002
|
6 |
M. Jun, K. Bang, H. Lee and E. Chung, 'Latency-aware bus arbitration for real-time embedded systems,' IEICE Trans. Inf. & Syst., vol.E90-D, no.3, 2007
|
7 |
K. Lee and Y. Yoon, 'Architecture exploration for performance improvement of SoC chip based on AMBA system,' ICCIT, pp.739-744, 2007
|
8 |
IBM, Armonk, NY, 'CoreConnect bus architecture,' 1999
|