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A High Performance NoC Architecture Using Data Compression  

Kim, Hong-Sik (연세대학교전기전자공학과)
Kim, Hyunjin (연세대학교전기전자공학과)
Hong, Won-Gi (대구대학교 정보통신공학과)
Kang, Sungho (연세대학교전기전자공학과)
Publication Information
IEMEK Journal of Embedded Systems and Applications / v.5, no.1, 2010 , pp. 1-6 More about this Journal
Keywords
NoC;
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  • Reference
1 J Kim, D, Park, T, Theocharides, N, Vijaykrishnan, and C. Das, "A low latency router supporting adaptivity for On-Chip Interconnects", Proc. of Design Automation Conference, pp. 559-564, Jun. 2005.
2 P. Guerrier and A. Greiner, "A generic architecture for On-Chip racket-switched interconnections", Proc. of Design and Test in Europe, pp. 250-256, Mar. 2000.
3 S. Kumar et al., "A network on chip architecture and design methodology", Proc. International Symposium on VLSI, pp. 117-124, 2002.
4 F, Karim et al, "An interconnect architecture for networking systems on chips", IEEE Micro, Vol.22, No.5, pp. 36-45, 2002.   DOI   ScienceOn
5 F, Moraes, N. Calazans, L. Moller, and L. Ost, "HERMES: An infrastructure for low area overhead packet-switching networks on chip", the VLSI integration, Vol.38, pp. 69-93, 2004.   DOI   ScienceOn
6 N, Eisley and L. -S. Phe, "High-level power analysis for on-chip networks", Proc. of CASES, pp, 104-115, Nov, 2004.
7 C, Erika, K F, Lima, C. Maico, A, Pedro, M. Paulo, A. Alexandre, L. Marcelo, "A high-fault-coverage approach for the test of data, control and gandshake interconnects in mesh networks-on-chip", IEEE Trans. Computers, Vol.57, No.9, pp. 1202-1215, 2008.   DOI
8 J. Duato and T, M, Prinkston, "A general theory for deadlock-free adaptive routing using a mixed set of resources", IEEE Trans. on Parallel Distributive Systems, Vol.12, No.12, pp, 1219-1235, 2001.   DOI   ScienceOn
9 A. Jalabert, S. Murali, L. Benini and G. D. Micheli, "Xpipes compiler: a tool for instantiating application specific networks on chip", Proc. of Design and Test in Europe, pp. 884-889, 2004.
10 R. F. Rice, "Some practical universal noiseless coding techniques", Jet Propulsion Laboratory, California Institute of Technology, Pasadena, Technical report, pp. 79-22, 1979.