• Korean Journal of Materials Research
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• v.15 no.5
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• pp.301-305
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• 2005

We fabricated nickel silicide layers on whole non-patterned wafers from $p-Si(100)SiO_2(200nm)$/poly-Si(70 nm)mn(40 nm) structure by 40 sec rapid thermal annealing of $500\~900^{\circ}C$. The sheet resistance, cross-sectional microstructure, surface roughness, and phase analysis were investigated by a four point probe, a field emission scanning electron microscope, a scanning probe microscope, and an X-ray diffractometer, respectively. Sheet resistance was as small as $7\Omega/sq$. even at the elevated temperature of $900^{\circ}C$. The silicide thickness and surface roughness increased as silicidation temperature increased. We confirmed the nickel silicides iron thin nickel/poly-silicon structures would be a mixture of NiSi and $NiSi_2$ even at the $NiSi_2$ stable temperature region.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.10-11
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• 2006

In this study, the Ni/Co/TiN (6/2/25 nm) structure was deposited for thermal stability estimation. Vacuum (30 mTorrs) annealing was carried out to compare with furnace annealing in nitrogen ambient. The proposed Ni/Co/TiN structure exhibited low temperature silicidation and wide range of rapid thermal process (RTP) windows. The sheet resistance was too high to measure after furnace annealing at $600^{\circ}C$ due to the thin thickness (15 nm) of the nickel silicide. However, the sheet resistance maintained stable characteristics up to $600^{\circ}C$ for 30 min after vacuum annealing. Therefore, the low resistance of thin film nickel silicide was obtained by vacuum annealing at $600^{\circ}C$.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.619-622
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• 2005

본 논문에서는 서로 다른 Si 두께 ($T_{Si}$ = 27, 50 nm) 를 갖는 SOI (Silicon On Insulator) 기판 위에 다양한 두께의 Ni/Co를 순차적으로 증착한 후 Bulk-Si과의 비교를 통해 Silicide의 형성 특성에 대하여 분석하였다. 우선 급속 열처리 (RTP, Rapid Thermal Processing) 를 통하여 Silicide를 형성한 후 측정결과 Si두께에 따라 Silicide의 특성이 달라짐을 확인하였다. 두꺼운 두께의 Si-film을 갖는 SOI 기판을 사용한 경우 증착된 금속의 두께에 따라 Bulk-Si와 비슷한 면저항 특성을 보였으나, 얇은 두께의 Si-film을 갖는 SOI기판을 사용한 경우에는 제한된 Si의 공급으로 인한 Silicide의 비저항 증가로 인하여 증착된 금속의 두께에 따라 면저항이 감소하다가 다시 증가하는 'V' 자형 곡선을 나타내었다.

• 한국신재생에너지학회:학술대회논문집
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• 2007.06a
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• pp.250-253
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• 2007

An evaporated Ti/Pd/Ag contact system is most widely used to make high-efficiency silicon solar cells, however, the system is not cost effective due to expensive materials and vacuum techniques. Commercial solar cells with screen-printed contacts formed by using Ag paste suffer from a low fill factor and a high shading loss because of high contact resistance and low aspect ratio. Low-cost Ni and Cu metal contacts have been formed by using electroless plating and electroplating techniques to replace the Ti/Pd/Ag and screen-printed Ag contacts. Ni/Cu alloy is plated on a silicon substrate by electro-deposition of the alloy from an acetate electrolyte solution, and nickel-silicide formation at the interface between the silicon and the nickel enhances stability and reduces the contact resistance. It was, therefore, found that nickel-silicide was suitable for high-efficiency solar cell applications. The Ni contact was formed on the front grid pattern by electroless plating followed by anneal ing at $380{\sim}400^{\circ}C$ for $15{\sim}30$ min at $N_{2}$ gas to allow formation of a nickel-silicide in a tube furnace or a rapid thermal processing(RTP) chamber because nickel is transformed to NiSi at $380{\sim}400^{\circ}C$. The Ni plating solution is composed of a mixture of $NiCl_{2}$ as a main nickel source. Cu was electroplated on the Ni layer by using a light induced plating method. The Cu electroplating solution was made up of a commercially available acid sulfate bath and additives to reduce the stress of the copper layer. The Ni/Cu contact was found to be well suited for high-efficiency solar cells and was successfully formed by using electroless plating and electroplating, which are more cost effective than vacuum evaporation. In this paper, we investigated low-cost Ni/Cu contact formation by electroless and electroplating for crystalline silicon solar cells.

• Korean Journal of Materials Research
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• v.11 no.9
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• pp.776-780
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• 2001

$SiO_2$ and polycrystalline Si layers were sequentially grown on (100) Si. NiSi was formed on this substrate from a 20nm Ni layer or a 20nm Ni/5nm Ti bilayer by rapid thermal annealing (RTA) at $300~500^{\circ}C$ to compare thermal stability. In addition, MOS capacitors were fabricated by depositing a 20nm Ni layer on the Poly-Si/$SiO_2$substrate, RTA at $400^{\circ}C$ to form NiSi, $BF_2$ or As implantation and finally drive- in annealing at $500~800^{\circ}C$ to evaluate electrical characteristics. When annealed at $400^{\circ}C$, NiSi made from both a Ni monolayer and a Ni/Ti bilayer showed excellent thermal stability. But NiSi made from a Ni/Ti bilayer was thermally unstable at $500^{\circ}C$. This was attributed to the formation of insignificantly small amount of NiSi due to suppressed Ni diffusion through the Ti layer. PMOS and NMOS capacitors made by using a Ni monolayer and the SADS(silicide as a dopant source) method showed good C-V characteristics, when drive-in annealed at $500^{\circ}C$ for 20sec., and$ 600^{\circ}C$ for 80sec. respectively.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.675-678
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• 2003

본 논문에서는 N-type 기판에서 Nickel-Silicide를 적용하였을 경우에 나타나는 문제점과 PAI (Pre-amorphization Implant)의 효과에 대하여 알아보았다. N-type 기판에 RTP (Rapid Thermal Process)를 통하여 Nickel-Silicide 를 형성하게 되는데, 여기까지는 안정한 Nickel mono-Silicide (NiSi)가 형성됨을 확인하였다. 하지만 후속 열처리 공정 후 심한 응집 현상 (Agglomeration)과 이상 산화 현상 (Abnormal Oxidation Phenomenon), Silicide Island 등 열안정성 (Thermal Stability) 측면에서 여러 가지 많은 문제점들이 나타났다. 이 후속 열처리의 열안정성 취약점들을 극복하는 방안으로 Ge 및 N₂ PAI를 적용하였다. PAI를 적용하였을 경우에는 그렇지 않은 경우에 비하여 고온 열처리 후에도 면저항이 비교적 잘 유지되었으며, 두께가 얇고 안정한 Nickel-Silicide 특성을 확보할 수 있었다. 특히 Ge PAI 에 비하여 N₂ PAI 의 경우가 보다 특성 개선 효과가 크게 나타났다.

• Journal of Powder Materials
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• v.6 no.2
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• pp.145-151
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• 1999

Nickel silicides ($Ni_5$Si$_2$, Ni$_2$Si and NiSi) have been synthesized by mechanical alloying (MA) of Ni-27.9at.9at%Si, Ni-33.3at% and Ni-50.0at% powder mixtures, respectively. From in situ thermal analysis, eash citical milling period for the formation of the three phases was observed to be 40.2, 34.9 and 57.5 min, at which there was a rapid increase in temperature. This indicates that rapid, self-propagating high-temperature synthesis (SHS) reactions were observed to produce the three phases during room-temperature high-energy ball milling of elemental powders. Each Ni silicide, Ni and Si, however, coexisted for an extended milling time even after the critical milling period. The powders mechanically alloyed after the critical period showed the rapid increase in microhardness. The Hv values were found to be higher than 1000kgf/mm$^2$. The formation of nickel silicides by mechanical alloying and the relevant reaction rates appeared to be influenced by the critical milling period and the heat of formation of the products involved ($Ni_5$Si$_2$$\rightarrow$-43.1kJ/mol.at., Ni$_2$Si$\rightarrow$-47.6kJ/mol.at., NiSi$\rightarrow$-42.4kJ/mol.at).

• Journal of the Korean institute of surface engineering
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• v.38 no.3
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• pp.89-94
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• 2005

We investigate the reaction stability of cobalt and nickel with side-wall materials of $SiO_2\;and\;Si_3N_4$. We deposited 15nm-Co and 15nm-Ni on $SiO_2(200nm)/p-type$ Si(100) and $Si_3N_4(70 nm)/p-type$ Si(100). The samples were annealed at the temperatures of $700\~1100^{\circ}C$ for 40 seconds with a rapid thermal annealer. The sheet resistance, shape, and composition of the residual materials were investigated with a 4-points probe, a field emission scanning electron microscopy, and an AES depth profiling, respectively. Samples of annealed above $1000^{\circ}C$ showed the agglomeration of residual metals with maze shape and revealed extremely high sheet resistance. The Auger depth profiling showed that the $SiO_2$ substrates had no residual metallic scums after $H_2SO_4$ cleaning while $Si_3N_4$ substrates showed some metallic residuals. Therefore, the $SiO_2$ spacer may be appropriate than $Si_3N_4$ for newly proposed Co/Ni composite salicide process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.7
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• pp.575-579
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• 2010

The technologies of Ni/Cu plating contact is attributed to the reduced series resistance caused by a better contact conductivity of Ni with Si and the subsequent electroplating of Cu on Ni. The ability to pattern narrower grid lines for reduced light shading was combined with the lower resistance of a metal silicide contact and an improved conductivity of the plated deposit. This improves the FF (fill factor) as the series resistance is reduced. This is very much requried in the case of low concentrator solar cells in which the series resistance is one of the important and dominant parameter that affect the cell performance. A Selective emitter structure with highly dopeds regions underneath the metal contacts, is widely known to be one of the most promising high-efficiency solution in solar cell processing In this paper the formation of a selective emitter, and the nickel silicide seed layer at the front side metallization of silicon cells is considered. After generating the nickel seed layer the contacts were thickened by Cu LIP (light induced plating) and by the formation of a plated Ni/Cu two step metallization on front contacts. In fabricating a Ni/Cu plating metallization cell with a selective emitter structure it has been shown that the cell efficiency can be increased by at least 0.2%.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.438-439
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• 2013

Microelectronic devices의 접촉저항의 향상을 위해 Metal silicides의 형성 mechanism과 전기적 특성에 대한 연구가 많이 이루어지고 있다. 지난 수십년에 걸쳐, Ti silicide, Co silicide, Ni silicide 등에 대한 개발이 이루어져 왔으나, 계속적인 저저항 접촉 소재에 대한 요구에 의해 최근에는 Rare earth silicide에 관한 연구가 시작되고 있다. Rare-earth silicide는 저온에서 silicides를 형성하고, n-type Si과 낮은 schottky barrier contact (~0.3 eV)를 이룬다. 또한, 비교적 낮은 resistivity와 hexagonal AlB2 crystal structure에 의해 Si과 좋은 lattice match를 가져 Si wafer에서 high quality silicide thin film을 성장시킬 수 있다. Rare earth silicides 중에서 ytterbium silicide는 가장 낮은 electric work function을 갖고 있어 낮은 schottky barrier 응용에서 쓰이고 있다. 이로 인해, n-channel schottky barrier MOSFETs의 source/drain으로써 주목받고 있다. 특히 ytterbium과 molybdenum co-deposition을 하여 증착할 경우 thin film 형성에 있어 안정적인 morphology를 나타낸다. 또한, ytterbium silicide와 마찬가지로 낮은 면저항과 electric work function을 갖는다. 그러나 ytterbium silicide에 molybdenum을 화합물로써 높은 농도로 포함할 경우 높은 schottky barrier를 형성하고 epitaxial growth를 방해하여 silicide film의 quality 저하를 야기할 수 있다. 본 연구에서는 ytterbium과 molybdenum의 co-deposition에 따른 silicide 형성과 전기적 특성 변화에 대한 자세한 분석을 TEM, 4-probe point 등의 다양한 분석 도구를 이용하여 진행하였다. Ytterbium과 molybdenum을 co-deposition하기 위하여 기판으로 $1{\sim}0{\Omega}{\cdot}cm$의 비저항을 갖는 low doped n-type Si (100) bulk wafer를 사용하였다. Native oxide layer를 제거하기 위해 1%의 hydrofluoric (HF) acid solution에 wafer를 세정하였다. 그리고 고진공에서 RF sputtering 법을 이용하여 Ytterbium과 molybdenum을 동시에 증착하였다. RE metal의 경우 oxygen과 높은 반응성을 가지므로 oxidation을 막기 위해 그 위에 capping layer로 100 nm 두께의 TiN을 증착하였다. 증착 후, 진공 분위기에서 rapid thermal anneal(RTA)을 이용하여 $300{\sim}700^{\circ}C$에서 각각 1분간 열처리하여 ytterbium silicides를 형성하였다. 전기적 특성 평가를 위한 sheet resistance 측정은 4-point probe를 사용하였고, Mo doped ytterbium silicide와 Si interface의 atomic scale의 미세 구조를 통한 Mo doped ytterbium silicide의 형성 mechanism 분석을 위하여 trasmission electron microscopy (JEM-2100F)를 이용하였다.