• Journal of Electrical Engineering and Technology
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• v.10 no.2
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• pp.496-503
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• 2015

In order to let a wind generator (WG) support the frequency control of a power system, a conventional inertial control algorithm using the rate of change of frequency (ROCOF) and frequency deviation loops was suggested. The ROCOF loop is prevailing at the initial stage of the disturbance, but the contribution becomes smaller as time goes on. Moreover, its contribution becomes negative after the frequency rebound. This paper proposes an inertial control algorithm of a wind power plant (WPP) using the maximum ROCOF and frequency deviation loops. The proposed algorithm replaces the ROCOF loop in the conventional inertial control algorithm with the maximum ROCOF loop to retain the maximum value of the ROCOF and eliminate the negative effect after the frequency rebound. The algorithm releases more kinetic energy both before and after the frequency rebound and increases the frequency nadir more than the conventional ROCOF and frequency loops. The performance of the algorithm was investigated under various wind conditions in a model system, which includes a doubly-fed induction generator-based WPP using an EMTP-RV simulator. The results indicate that the algorithm can improve the frequency drop for a disturbance by releasing more kinetic energy.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.2
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• pp.133-138
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• 2017

This paper presents a jitter characteristic improved phase locked loop (PLL) with an RC time constant circuit. In the RC time constant circuit, LPF's voltage is inputted to a comparator through small and large RC time constant circuits. The signal through a small RC time constant circuit has almost same loop filter output voltage. The signal through a large RC time constant circuit has the average value of loop filter output voltage and does as a role of reference voltage to the comparator. The output of the comparator controls the sub-charge pump which provide a current to LPF. When the loop filter output voltage increases, the sub-charge pump discharges the loop filter and decreases loop filter output voltage. When the loop filter output voltage decreases, the sub-charge pump charges the loop filter and increases loop filter output voltage. The negative feedback loop reduces the variation of loop filter output voltage resulting in jitter characteristic improvement.

• Journal of the Korean Society of Safety
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• v.35 no.2
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• pp.34-46
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• 2020

Unlike research focused on existing technologies and individual errors to analyze the causes of incidents, this study approached them from an organization and culture. And this study is not a one way study but cyclical study what can track cause down using causal loop diagram methodology. Four diagnostic criteria for the negative state of the safety culture : secretive, blame, failure to learning, and incremental learning, combine literature study and expert opinion to derive 41 variables. Connecting these variable make 4 causal loop diagrams and total causal loop diagram. Case accumulation in secretive, accident report in blame, knowledge accumulation in failure to learning, near miss discovery in incremental learning are the main variables. Safety incident is the objective variable by classifying them into 4 stages in total loop, leading track as the most affect is case accumulation, and Step 4 as you can see accident report and near miss discovery are the result of tracking down the cause. This study can be used as a basis for improving the management priority and the system in incident prevention.

• Journal of international Conference on Electrical Machines and Systems
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• v.3 no.2
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• pp.155-161
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• 2014

Industrial Static Var Generator (SVG) is typically applied at or near the load center to mitigate voltage fluctuation, flicker, phase unbalance, non-sine distortion or other load-related disturbance. Special attention is paid to the influence of grid voltage quality on SVG current, the non-sine distortion and unbalance of grid voltage causes not only the AC current distortion and unbalance but also the DC voltage fluctuation. In order to let the inverter voltage contain the fundamental negative sequence and harmonic component corresponding to the grid voltage, a new dual-loop control scheme is proposed to suppress the influence in this paper. The harmonic and negative sequence voltage decomposition algorithm and DC voltage control are also introduced. All these analyses can guide the practical applications. The simulation results verify the feasibility and effectiveness of the present control strategy and analyses.

• 제어로봇시스템학회:학술대회논문집
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• 1987.10b
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• pp.198-202
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• 1987

The regulator problem can be considered as some impulsive disturbance rejection one. In this point of view, the rate of decay is one of important factors for regulation and depends on how negative the real parts of the eigenvalues of closed-loop system. The algorithm that the closed-loop system has eigenvalues lying within a vertical. strip is useful for rapid disturbance rejection. This paper presents a design method for a linear quadratic regulator of two-time scale system with eigenvalues in a vertical strip by use of time-scale separation property.

• Proceedings of the Microbiological Society of Korea Conference
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• 2005.05a
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• pp.211.1-211
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• 2005

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.819-825
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• 2016

In this paper, a phase locked loop structure with parallel dual loop which have a different bandwidth has been proposed. The bandwidths depending on transfer functions are obtained through dual loops. Two different bandwidths of each loop are used to suppress noise on the operating frequency range. The proposed phase locked loop has two different voltage controlled oscillator gains to control two different wide and narrow loop filters. Furthermore, it has the locking status indicator to achieve an accurate locking condition. The phase margin of $58.2^{\circ}$ for wide loop and $49.4^{\circ}$ for narrow loop is designed for stable operation and the phase margin of $45^{\circ}$ is maintained during both loops work together. It has been designed with a 1.8V 0.18um complementary metal oxide semiconductor (CMOS) process. The simulation results show that the proposed phase locked loop works stably and generates a target frequency.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.457-462
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• 2014

This letter proposes a low-jitter DLL-based clock generator with two negative feedback loops. The main negative feedback loops suppress the jitter of DLL. The additional negative feedback loops suppress the delay-time variance of each delay stages. Both two negative feedback loops in a DLL results in suppressing the jitter of clock signal further. Measurement results of the DLL-based clock generator with two negative feedback loops fabricated in a one-poly six-metal $0.18{\mu}m$ CMOS process show 5.127-ps rms jitter and 47.6-ps peak-to-peak jitter at 1 GHz.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.68-77
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• 2003

An improved negative capacitance circuit that cancels out input impedance of a front-end in a bioimpedance measurement and operates stably with a low gain margin has been proposed. Since the proposed circuit comprises wide-band operational amplifiers, selecting operational amplifiers is easy, while an operational amplifier of prefer bandwidth should be chosen to apply conventional circuit. Also, since gain margin can be controlled by a feedback resistor connected serially with a feedback capacitor, gain margin is tuneable with a potentiometer. The input impedance of the proposed circuit is two times larger than that of the conventional circuit and 40-times than that without a negative capacitance circuit. Furthermore, closed-loop phase response of the proposed circuit is better than that of the conventional circuit or without a negative capacitance circuit. Above all, for the proposed circuit, the frequency at which a gain peaking occurs is higher than the frequency at which the loop gain becomes a maximum. Thus, the proposed circuit is not affected by a gain peaking and can be operated with a very low gain margin.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.2
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• pp.152-159
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• 2015

In a weak grid condition, the precise grid impedance estimation is essential to guaranteeing the high performance current control and power transfer for a grid-connected inverter. This study proposes a precise estimation method for grid impedance by PQ variations by employing the variation method of reference currents. The operation principle of grid impedance estimation is fully presented, and the negative impact of the phase locked loop is analyzed. Estimation error by a synchronization angle in the park's transformation using the phase locked loop is derived. As a result, the variation method of reference currents for accurate estimation is introduced. The validation of the proposed method is verified through several simulation results and experiments based on a 2-kW voltage source inverter prototype.