• 전기학회논문지
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• 제66권10호
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• pp.1494-1498
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• 2017

In this study, we investigate the influence of an overlap between the gate and source/drain regions of silicon nanowire (SiNW) CMOS (complementary metal-oxide-semiconductor) inverter on bendable plastic substrates and describe their electrical characteristics. The combination of n-channel silicon nanowire field-effect transistor (n-SiNWFET) and p-channel silicon nanowire field-effect transistor (p-SiNWFET) operates as an inverter logic gate. The gains with a drain voltage ($V_{dd}$) of 1 V are 3.07 and 1.21 for overlapped device and non-overlapped device, respectively. The superior electrical characteristics of each of the SiNW transistors including steep subthreshold slopes and the high $I_{on}/I_{off}$ ratios are major factors that enable the excellent operation of the logic gate.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권2호
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• pp.185-190
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• 2016

A 70-${\AA}$ nanowire field-effect transistor (FET) for sub-10-nm CMOS technology is designed and simulated in order to investigate the impact of an oxide trap on random telegraph noise (RTN) in the device. It is observed that the drain current fluctuation (${\Delta}I_D/I_D$) increases up to a maximum of 78 % due to the single electron trapping. In addition, the effect of various trap positions on the RTN in the nanowire FET is thoroughly analyzed at various drain and gate voltages. As the drain voltage increases, the peak point for the ${\Delta}I_D/I_D$ shifts toward the source side. The distortion in the electron carrier density and the conduction band energy when the trap is filled with an electron at various positions in the device supports these results.

• EDISON SW 활용 경진대회 논문집
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• 제3회(2014년)
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• pp.434-438
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• 2014

CMOS의 최종형태로써 Gate-All-Around(GAA) Silicon Nanowire(NW)가 각광받고 있다. 이 논문에서 NW FET(Field Effect Transistor)의 채널 길이와 NW의 폭과 같은 size에 따른 특성변화를 실제 실험 data와 NW FET 특성분석 simulation을 이용해서 비교해보았다. MOSFET(Metal Oxide Semiconductor Field Effect Transistor)의 소형화에 따른 쇼트 채널 효과(short channel effect)에 의한 threshold voltage($V_{th}$), Drain Induced Barrier Lowering(DIBL), subthreshold swing(SS) 또한 비교하였다. 이에 더하여, 기존의 상용툴로 NW를 해석한 시뮬레이션 결과와도 비교해봄으로써 NW의 size scaling에 대한 EDISON NW 해석 simulation의 정확도를 파악해보았다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권2호
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• pp.152-159
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• 2010

We propose a semi-analytical current conduction model for depletion-mode n-type nanowire field-effect transistors (NWFETs) with top-gate structure. The NWFET model is based on an equivalent circuit consisting of two back-to-back Schottky diodes for the metal-semiconductor (MS) contacts and the intrinsic top-gate NWFET. The intrinsic top-gate NWFET model is derived from the current conduction mechanisms due to bulk charges through the center neutral region as well as of accumulation charges through the surface accumulation region, based on the electrostatic method, and thus it includes all current conduction mechanisms of the NWFET operating at various top-gate bias conditions. Our previously developed Schottky diode model is used for the MS contacts. The newly developed model is integrated into ADS, in which the intrinsic part of the NWFET is developed by utilizing the Symbolically Defined Device (SDD) for an equation-based nonlinear model. The results simulated from the newly developed NWFET model reproduce considerably well the reported experimental results.

• Transactions on Electrical and Electronic Materials
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• 제14권3호
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• pp.156-159
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• 2013

The electrical properties of ZnO nanowire field effect transistors (FETs) have been investigated depending on various diameters of nanowires. The ZnO nanowires were synthesized with an Au catalyst on c-plane $Al_2O_3$ substrates using hot-walled pulsed laser deposition (HW-PLD). The nanowire FETs are fabricated by conventional photo-lithography. The diameter of ZnO nanowires is simply controlled by changing the thickness of the Au catalyst metal, which is confirmed by FE-SEM. It has been clearly observed that the ZnO nanowires showed different diameters simply depending on the thickness of the Au catalyst. As the diameter of ZnO nanowires increased, the threshold voltage of ZnO nanowires shifted to the negative direction systematically. The results are attributed to the difference of conductive layer in the nanowires with different diameters of nanowires, which is simply controlled by changing the catalyst thickness. The results show the possibility for the simple method of the fabrication of nanowire logic circuits using enhanced and depleted mode.

• 대한전자공학회논문지SD
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• 제45권4호
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• pp.49-56
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• 2008

본 논문은 효율적인 회로 시뮬레이션을 위한 긴 채널 공핍 모드 n형 나노선 전계효과트랜지스터(nanowire field-effect transistor: NWFET)의 간단한 해석적 전류 전도 모델을 소개한다. 본 연구에서 사용된 NWFET는 bottom-up 방식으로 제작되었으며 게이트가 채널의 아래에 존재하는 구조를 가진다. 이 모델은 다양한 바이어스 조건에서 동작하는 NWFET의 모든 전류 전도 메카니즘을 포함한다. 새롭게 개발된 NWFET 모델로 계산된 결과는 이전에 발표된 NWFET 실험 데이터와 비교할 때 10% 오차범위 안에서 서로 일치한다.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2007년도 추계학술발표대회 및
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• pp.64.1-64.1
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• 2007

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2018년도 추계학술대회
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• pp.381-382
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• 2018

무접합 나노선 터널 전계 효과 트렌지스터(junctionless nanowire tunnel field-effect transistor; JLNW-TFET)에서 소스(p+), 채널(i), 드레인(n) 물질으로 실리콘 및 게르마늄을 사용하여 이 구조에 대한 문턱전압 이하 기울기(subthreshold swings; SS)와 구동전류를 관찰했다. 소스-채널을 게르마늄-실리콘일 때 실리콘-실리콘, 실리콘-게르마늄, 게르마늄-게르마늄 구조보다 구동전류가 최대 1000배 증가하였고, 실리콘-실리콘 구조가 다른 구조에 비해 최소 SS가 최대 5배 이상 감소하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.413-413
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• 2009

Silicon nanowires (Si NWs)-based top-gate field-effect transistors (FETs) are constructed by using Si NWs transferred onto flexible plastic substrates. Si NWs are obtained from the silicon wafers using photolithography and anisotropic etching process, and transferred onto flexible plastic substrates. To evaluate the electrical performance of the silicon nanowires, we examined the output and transfer characteristics of a top-gate field-effect transistor with a channel composed of a silicon nanowire selected from the nanowires on the plastic substrate. From these FETs, a field-effect mobility and transconductance are evaluated to be $47\;cm^2/Vs$ and 272 nS, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권4호
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• pp.361-366
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• 2013

A full-range analytic drain current model for depletion-mode long-channel surrounding-gate nanowire field-effect transistor (SGNWFET) is proposed. The model is derived from the solution of the 1-D cylindrical Poisson equation which includes dopant and mobile charges, by using the Pao-Sah gradual channel approximation and the full-depletion approximation. The proposed model captures the phenomenon of the bulk conduction mechanism in all regions of device operation (subthreshold, linear, and saturation regions). It has been shown that the continuous model is in complete agreement with the numerical simulations.