• Journal of the Korean Institute of Intelligent Systems
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• v.20 no.6
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• pp.761-767
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• 2010

In the case of NAND flash memory, a whole block needs to be erased for update operations because update-in- place operations are not supported in NAND flash memory. Blocks of NAND flash memory have the limited erasure cycles, so frequently updated data (hot data) easily makes blocks worn out. As the result, the capacity of NAND flash memory will be reduced by hot data. In this paper, we propose a wear-leveling algorithm by discriminating hot and cold data based on the update patterns of data. When we applied this scheme to NAND flash memory, we confirmed that the erase counts of blocks became more uniform by mapping hot data to a block with a low erase count and cold data to block with a high erase count.

• Journal of Information Processing Systems
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• v.2 no.3 s.4
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• pp.147-152
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• 2006

NAND flash memory-based embedded systems are becoming increasingly common. These embedded systems have to provide a fast boot time. In this paper, we have designed and proposed a flash file system for embedded systems that require fast booting. By using a Flash Image Area, which keeps the latest flash memory information such as types and status of all blocks, the file system mounting time can be reduced significantly. We have shown by experiments that our file system outperforms YAFFS and RFFS.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.4
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• pp.177-185
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• 2005

NAND-type flash memory is becoming increasingly popular as a large data storage for mobile computing devices. Since flash memory is an order of magnitude more expensive than magnetic disks, data compression can be effectively used in managing flash memory based storage systems. However, compressed data management in NAND-type flash memory is challenging because it supports only page-based I/Os. For example, when the size of compressed data is smaller than the page size. internal fragmentation occurs and this degrades the effectiveness of compression seriously. In this paper, we present an efficient flash compression layer (FCL) for NAND-type flash memory which stores several small compressed pages into one physical page by using a write buffer Based on prototype implementation and simulation studies, we show that the proposed scheme offers the storage of flash memory more than $140\%$ of its original size and expands the write bandwidth significantly.

• KIPS Transactions on Computer and Communication Systems
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• v.5 no.1
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• pp.1-6
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• 2016

This paper focuses on algorithm innovation of NAND Flash Memory for enhancing cell lifetime. During flash memory read/write/erase, the voltage of a specific cell should be a valid voltage level. If not, we cannot read the data correctly. This type of interference/disturbance tends to be serious when program and erase operation will go on. This is because FN tunneling results in tunnel oxide damage due to increased trap site on repetitive high biased state. In order to resolve this problem, we make the cell degradation by reducing the amount of stress in terms of erase cell, resulting in minimizing the cell disturbance on erase verify.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.2
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• pp.275-282
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• 2015

Since a NAND-flash memory is able to keep data during electricity-off and has small cost to store data per bytes, it is widely used on hand-held devices. It is necessary to use an index in order to process mass data effectively on the flash memory. However, since the flash memory requires high cost for a write operation and does not support an overwrite operation, it is possible to reduce the performance of the index when the disk based index is exploited. In this paper, we implement the fixed grid file index and evaluate the performance of the index on various conditions. To do this, we measure the average processing time by the ratio of query operations and update operations. We also the compare the processing times of the flash memory with those of the magnetic disk.

• IEMEK Journal of Embedded Systems and Applications
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• v.18 no.1
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• pp.31-40
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• 2023

Recent advances in flash technologies, such as 3D processing and multileveling schemes, have successfully increased the flash capacity. Unfortunately, these technology advances significantly degrade flash's reliability due to a smaller cell geometry and a finer-grained cell state control. In this paper, we propose an asymmetric BER-aware reliability optimization technique (aBARO), new flash optimization that improves the flash reliability. To this end, we first reveal that bit errors of 3D NAND flash memory are highly skewed among flash cell states. The proposed aBARO exploits the unique per-state error model in flash cell states by selecting the most error-prone flash states and by forming narrow threshold voltage distributions (for the selected states only). Furthermore, aBARO is applied only when the program time (tPROG) gets shorter when a flash cell becomes aging, thereby keeping the program latency of storage systems unchanged. Our experimental results with real 3D MLC and TLC flash devices show that aBARO can effectively improve flash reliability by mitigating a significant number of bit errors. In addition, aBARO can also reduce the read latency by 40%, on average, by suppressing the read retries.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.8A
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• pp.706-711
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• 2012

Multi-level cell NAND flash is a flash memory technology using multiple levels per cell to allow more bits to be stored. Currently, most multi-level cell NAND stores 2 bits of information per cell. This reduces the amount of margin separating the states and results in the possibility of more errors. The most error cause is coupling noise. Thus, in this paper, we studied coupling noise cancellation scheme for reduction memory on the 16-level cell NAND flash memory channel. Also, we compared the performance threshold detection and proposed scheme.

• Journal of IKEEE
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• v.25 no.4
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• pp.770-773
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• 2021

In this paper, the retention characteristics of 3D NAND flash memory applied with tapering and ferroelectric (HfO₂) structure were analyzed after programming operation. Electrons trapped in nitride are affected by lateral charge migration over time. It was confirmed that more lateral charge migration occurred in the channel thickened by tapering of the trapped electrons. In addition, the Oxide-Nitride-Ferroelectric (ONF) structure has better lateral charge migration due to polarization, so the change in threshold voltage (V_th) is reduced compared to the Oxide-Nitride-Oxide (ONO) structure.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.1
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• pp.23-28
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• 2023

This paper demonstrates a novel NAND flash memory structure and annealing configuration including through-silicon via (TSV) inside the silicon substrate to improve annealing efficiency using an electro-thermal annealing (ETA) technique. Compared with the conventional ETA which utilizes WL-to-WL current flow, the proposed annealing method has a higher annealing temperature as well as more uniform heat distribution, because of thermal isolation on the silicon substrate. In addition, it was found that the annealing temperature is related to the electrical and thermal conductivity of the TSV materials. As a result, it is possible to improve the reliability of NAND flash memory. All the results are discussed based on 3-dimensional (3-D) simulations with the aid of the COMSOL simulator.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.47 no.5
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• pp.35-40
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• 2010

NAND flash memory has been widely used than traditional HDD in PDA and other mobile devices, embedded systems, PC because of faster access speed, low power consumption, vibration resistance and other benefits. DiskSim and other HDD simulators has been developed that for find improvements for the software or hardware. But there is a few Linux-based simulators for NAND flash memory and SSD. There is necessary for Windows-based NAND flash simulator because storage devices and PC using Windows. This paper describe for development of simulator-NFSim for FTL performance analysis in NAND flash. NFSim is used to measure performance of various FTL algorithms and FTL wear-level. NAND flash memory model and FTL algorithm developed using Windows Driver Model and class for scalability. There is no need for another tools because NFSim using graph tool for data measure of FTL performance.