• Journal of Satellite, Information and Communications
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• v.8 no.4
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• pp.124-129
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• 2013

An electrostatic discharge (ESD) protection device, so called, N-type SCR with P-type MOSFET pass structure (NSCR_PPS), was analyzed for high voltage I/O applications. A conventional NSCR_PPS device shows typical SCR-like characteristics with extremely low snapback holding voltage, which may cause latch-up problem during normal operation. However, a modified NSCR_PPS device with counter pocket source(CPS) and partial p-type well(PPW) structure demonstrates highly latch-up immune current-voltage characteristics.

• Journal of the Korean Institute of Telematics and Electronics
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• v.19 no.1
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• pp.9-13
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• 1982

The purpose of this experiment is to evaluate the noise dependency on the gate dimensions of the P-ch MOSFET which is fabricated of p+ sourse, drain, and gate electrode doped with PH$_3$ gas in type-N Si sudstrate. Experimental results indicate that: for the constant gate area and reletively thick films, noise level tends to decrease for the W/L ratio over unity, which generally conforms with theoretical observations, but its variation with the change in the thickness of film is less than the theoretically predicted for the W/L ratio below unity.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.150-151
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• 2006

$Si_{0.88}Ge_{0.12}$/Si heterostructure channels grown by RPCVD were employed to n-type metal oxide semiconductor field effect transistors(MOSFETs), and their electrical properties were investigated. SiGe nMOSFETs presented very high transconductance compared to conventional Si-bulk MOSFETs, regardless substantial drawbacks remaining in subthreshold-slope, $I_{off}$, and leakage current level. It looks worthwhile to utilize excellent transconductance properties into rf applications requesting high speed and amplification capability, although optimization works on both device structure and unit processes are necessary for enhanced isolation and reduced power dissipation.

• Korean Journal of Materials Research
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• v.18 no.5
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• pp.272-276
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• 2008

In submicron MOSFET devices, maintaining the ratio between the channel length (L) and the channel depth (D) at 3 : 1 or larger is known to be critical in preventing deleterious short-channel effects. In this study, n-type SOI-MOSFETs with a channel length of $0.1\;{\mu}m$ and a Si film thickness (channel depth) of $0.033\;{\mu}m$ (L : D = 3 : 1) were virtually fabricated using a TSUPREM-4 process simulator. To form functioning transistors on the very thin Si film, a protective layer of $0.08\;{\mu}m$-thick surface oxide was deposited prior to the source/drain ion implantation so as to dampen the speed of the incoming As ions. The p-type boron doping concentration of the Si film, in which the device channel is formed, was used as the key variable in the process simulation. The finished devices were electrically tested with a Medici device simulator. The result showed that, for a given channel doping concentration of $1.9{\sim}2.5\;{\times}\;10^{18}\;cm^{-3}$, the threshold voltage was $0.5{\sim}0.7\;V$, and the subthreshold swing was $70{\sim}80\;mV/dec$. These value ranges are all fairly reasonable and should form a 'magic region' in which SOI-MOSFETs run optimally.

• Nuclear Engineering and Technology
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• v.52 no.8
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• pp.1764-1770
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• 2020

The present work was mainly concerned with studying the operation of RC-phase shift oscillator based on MOSFET type 2N6660 under the influence of different temperature levels ranging from room temperature (25 ℃) up-to135 ℃ and gamma-irradiation up-to 3.5 kGy. In this concern, both the static (I-V) characteristic curves of MOSFET devices and the output signal of the proposed oscillator were recorded under ascending levels of both temperature and gamma-irradiation. From which, it is clearly shown that the drain current was decreased from 0.22 A, measured at 25 ℃, down to 0.163 A, at 135 ℃. On the other hand, its value was increased up-to 0.49 A, whenever the device was exposed to gamma-rays dose of 3.5 kGy. Considering RC-phase shift oscillator, the oscillation frequency and output pk-pk voltage were decreased whenever MOSFET device exposed to gamma radiation by ratio 54.9 and 91%, respectively. While, whenever MOSFET device exposed to temperature the previously mentioned parameters were shown to be decreased by ratio 2.07 and 46.2%.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1372-1373
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• 2006

An electrostatic discharge (ESD) protection device, so called, N-type SCR with P-type MOSFET pass structure (NSCR_PPS), was analyzed for high voltage I/O applications. A conventional NSCR_PPS device shows typical SCR-like characteristics with extremely low snapback holding voltage, which may cause latchup problem during normal operation. However, a modified NSCR_PPS device with proper junction/channel engineering demonstrates highly latchup immune current- voltage characteristics.

• Journal of Sensor Science and Technology
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• v.20 no.3
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• pp.156-161
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• 2011

We fabricated a schottky barrier metal oxide semiconductor field effect transistor(SB-MOSFET) by applying indium-tin-oxide(ITO) to the source/drain on a highly resistive GaN layer grown on a silicon substrate. The MOSFET, with 10 ${\mu}M$ gate length and 100 ${\mu}M$ gate width, exhibits a threshold gate voltage of 2.7 V, and has a sub-threshold slope of 240 mV/dec taken from the $I_{DS}-V_{GS}$ characteristics at a low drain voltage of 0.05 V. The maximum drain current is 18 mA/mm and the maximum transconductance is 6 mS/mm at $V_{DS}$=3 V. We observed that the spectral photo-response characterization exhibits that the cutoff wavelength was 365 nm, and the UV/visible rejection ratio was about 130 at $V_{DS}$ = 5 V. The MOSFET-type UV detector using ITO, has a high UV photo-responsivity and so is highly applicable to the UV image sensors.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.12
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• pp.1870-1877
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• 1990

The electromagnetic properties of P- and n-channel split drain magnetic sensitive MOSFET fabricated using 2\ulcorner design rules and CMOS process technology has been investigated. The achieved output voltage in the double drain MOSFET was 160mV at 10\ulcorner drain current and magnetic flux density of 10kG, and the sensitivity was 1.6x10**3 V/A\ulcornerG. A further higher sensitivity was obtained by introducing a third drain in the split region. In this case, the triple drain MOSFET showed a much higher sensitivity of 2x10**3 V/A\ulcornerG under the same condition. Also, the linearity of output voltage vs. magnetic flux density was excellent.

• Proceeding of EDISON Challenge
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• 2017.03a
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• pp.428-432
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• 2017

Silicon 기반 Metal-oxide-semiconductor field-effect transistor (MOSFET)의 크기가 감소함에 따라 silicon자체의 물성적 한계가 나타나고 있다. 이를 극복하고자 III-V 화합물 반도체가 채널소자로서 각광받고 있다. 본 연구에서는 III-V 화합물반도체 중 $In_xGa_{1-x}As$는 Indium 조성에 따른 전자구조 및 n-type MOSFET의 소자 특성을 본다. Indium의 조성이 증가함에 따라 subband의 개수와 간격이 증가하게 되어 Density of state가 감소하게 된다. 이로 인하여 Indium의 조성이 증가함에 따라 $In_xGa_{1-x}As$ 채널 MOSFET에서 상대적으로 Fermi level을 더 많이 상승시키게 되어 potential barrier를 얇아지게 만들며 또한 에너지에 따른 전류 밀도를 넓게 분포하도록 만든다. 이로 인하여 단채널에서는 In 조성이 증가함에 따라 direct source-to-drain tunnelling current이 증가하게 된다. 이로 인하여 In 조성의 증가에 따라 subthreshold swing과 ON-state current가 저하된다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.7
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• pp.584-592
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• 2003

6H-SiC MOSFETs and digital ICs have been fabricated and characterized. PMOS devices are fabricated on an n-type epilayer while the NMOS devices are fabricated on implanted p-wells. NMOS and PMOS devices use a thermally grown gate oxide. SiC MOSFETs are fabricated using different impurity activation methods such as high temperature and newly proposed laser annealing methods. Several digital circuits, such as resistive road NMOS inverters, CMOS inverters, resistive road NMOS NANDs and NORs are fabricated and characterized.