• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.9-15
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• 2003

An optimized finite-field multiplier is proposed for encryption and error correction devices. It is based on a modified Linear Feedback Shift Register (LFSR) which has lower power consumption and smaller area than prior LFSR-based finite-field multipliers. The proposed finite field multiplier for GF(2n) multiplies two n-bit polynomials using polynomial basis to produce $z(x)=a(x)^*b(x)$ mod p(x), where p(x) is a irreducible polynomial for the Galois Field. The LFSR based on a serial multiplication structure has less complex circuits than array structures and hybrid structures. It is efficient to use the LFSR structure for systems with limited area and power consumption. The prior finite-field multipliers need 3${\cdot}$m flip-flops for multiplication of m-bit polynomials. Consequently, they need 6${\cdot}$m latches because one flip-flop consists of two latches. The proposed finite-field multiplier requires only 4${\cdot}$m latches for m-bit multiplication, which results in 1/3 smaller area than the prior finite-field multipliers. As a result, it can be used effectively in encryption and error correction devices with low-power consumption and small area.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.35-41
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• 2020

Fast Fourier transform (FFT) processors have been widely used in various application such as communications, image, and biomedical signal processing. Especially, high-performance and low-power FFT processing is indispensable in OFDM-based communication systems. This paper presents a novel radix-26 FFT algorithm with low computational complexity and high hardware efficiency. Applying a 7-dimensional index mapping, the twiddle factor is decomposed and then radix-26 FFT algorithm is derived. The proposed algorithm has a simple twiddle factor sequence and a small number of complex multiplications, which can reduce the memory size for storing the twiddle factor. When the coefficient of twiddle factor is small, complex constant multipliers can be used efficiently instead of complex multipliers. Complex constant multipliers can be designed more efficiently using canonic signed digit (CSD) and common subexpression elimination (CSE) algorithm. An efficient complex constant multiplier design method for the twiddle factor multiplication used in the proposed radix-26 algorithm is proposed applying CSD and CSE algorithm. To evaluate performance of the previous and the proposed methods, 256-point single-path delay feedback (SDF) FFT is designed and synthesized into FPGA. The proposed algorithm uses about 10% less hardware than the previous algorithm.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 2004.04a
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• pp.17-24
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• 2004

This paper established the dynamic model of a flexible Timoshenko beam with geometrical nonlinearities subject to large overall motions by using the finite element method. The equations of motion are derived by using Hamilton principle based on expressing the kinetic and potential energies of the flexible beam in terms of generalized coordinates. The nonlinear constraint equations are adjoined to the system equations of motion by using Lagrange multipliers.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.149-152
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• 2000

A dual-mode multiplier (DMM) that performs single- and double-precision multiplications has been designed. An algorithm for efficiently implementing double-precision multiplication with a single-precision multiplier was proposed, which is based on partitioning double-precision multiplication into four single-precision sub-multiplications and computing them with sequential accumulations. When compared with conventional double-precision multipliers, our approach reduces the hardware complexity by about one third resulting in small silicon area and low-power dissipation at the expense of increased latency and throughput cycles.

• Proceedings of the IEEK Conference
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• 2000.06c
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• pp.85-88
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• 2000

This paper describes the design of multiplier that receives two N-bit number and produces an N-bit product, with leading 0/l detector logic for an overflow prediction. A leading 0/l detector for two's input predict a scope of output. The part of partial products sum of N most-significant bits is exchanged for an overflow prediction. Therefore this multiplier requires less gates for the implementation about 45% than general multipliers.

• Journal of the Korean Data and Information Science Society
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• v.14 no.2
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• pp.337-343
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• 2003

In this paper we present the prediction interval estimation method using bootstrap method for least squares support vector machine(LS-SVM) regression, which allows us to perform even nonlinear regression by constructing a linear regression function in a high dimensional feature space. The bootstrap method is applied to generate the bootstrap sample for estimation of the covariance of the regression parameters consisting of the optimal bias and Lagrange multipliers. Experimental results are then presented which indicate the performance of this algorithm.

• Bulletin of the Korean Mathematical Society
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• v.55 no.4
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• pp.1137-1147
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• 2018

In this paper, we discovered a sufficient condition ensuring the weighted composition operators $C_{{\omega}_1,{\varphi}_1},{\cdots},C_{{\omega}_N,{\varphi}_N}$ were disjoint supercyclic on $H({\Omega})$ endowed with the compact open topology. Besides, we provided a condition on inducing symbols to guarantee the disjoint supercyclicity of non-constant adjoint multipliers $M^*_{{\varphi}_1},M^*_{{\varphi}_2},{\cdots},M^*_{{\varphi}_N}$ on a Hilbert space ${\mathcal{H}}$.

• Bulletin of the Korean Mathematical Society
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• v.47 no.4
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• pp.839-857
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• 2010

We give a set of continuous characterizations for the homogeneous Triebel-Lizorkin spaces and use them to study boundedness properties of Fourier multiplier operators whose symbols satisfy a generalization of H$\ddot{o}$rmander's condition. As an application, we give new direct proofs of the imbedding theorems of the Sobolev type.

• Bulletin of the Korean Mathematical Society
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• v.51 no.1
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• pp.267-285
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• 2014

An upstream scheme based on the pseudostress-velocity mixed formulation is studied to solve convection-dominated Oseen equations. Lagrange multipliers are introduced to treat the trace-free constraint and the lowest order Raviart-Thomas finite element space on rectangular mesh is used. Error analysis for several quantities of interest is given. Particularly, first-order convergence in $L^2$ norm for the velocity is proved. Finally, numerical experiments for various cases are presented to show the efficiency of this method.

• Journal of information and communication convergence engineering
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• v.6 no.3
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• pp.289-293
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• 2008

In this paper, we propose the hardware architecture to accelerate 2D Vector graphics process for mobile devices. we propose the Transformation Unit Architecture that considerates the operation dependency. It has 3 cycles excution time and uses 2 multipliers and 2 adders. Proposed paint generation unit uses a LUT method, so it does not execute color interpolation which needs to be calculated every time. The proposed OpenVG 1.0 Accelerator achieved a 2.85 times faster performance in a tiger model.