Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2000.06c
- /
- Pages.85-88
- /
- 2000
A Multiplier with Leading 0/1 Detector
Leading 0/1 검출 기능을 부가한 곱셈기
Abstract
This paper describes the design of multiplier that receives two N-bit number and produces an N-bit product, with leading 0/l detector logic for an overflow prediction. A leading 0/l detector for two's input predict a scope of output. The part of partial products sum of N most-significant bits is exchanged for an overflow prediction. Therefore this multiplier requires less gates for the implementation about 45% than general multipliers.
Keywords