• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.129-136
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• 2005

A multiplier generator, VPM_Gen (Variable-Precision Multiplier Generator), which generates Verilog-HDL models of multiplier cores with user-defined bit-width specification, is described. The bit-widths of operands are parameterized in the range of $8-bit{\sim}32-bit$ with 1-bit step, and the product from multiplier core can be truncated in the range of $8-bit{\sim}64-bit$ with 2-bit step, resulting that the VPM_Gen can generate 3,455 multiplier cores. In the case of truncating multiplier output, by eliminating the circuits corresponding to the truncation part, the gate counts and power dissipation can be reduced by about 40% and 30%, respectively, compared with full-precision multiplier. As a result, an area-efficient and low-power multiplier core can be obtained. To minimize truncation error, an adaptive error-compensation method considering the number of truncation bits is employed. The multiplier cores generated by VPM_Gen have been verified using Xilinx FFGA board and logic analyzer.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.5
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• pp.747-755
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• 1990

In this paper, we presented a method of constructing a multiplier and an inverse element generator over finite field GF(3**m). We proposed the multiplication method using a descending order arithmetics of mod F(X) to perform the multiplication and mod F(X) arithmetics at the same time. The proposed multiplier is composed of following parts. 1) multiplication part, 2) data assortment generation part and 5) multiplication processing part. Also the inverse element generator is constructed with following parts. 1) multiplier, 2) group of output registers Rs, 3) multiplication and cube selection gate Gl, 4) Ri term sequential selection part. 5) cube processing part and 6) descending order mod F(X) generation part. Especially, the proposed multiplier and inverse element generator give regularity, expansibility and modularity of circuit design.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.285-291
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• 2001

An 8-b$\times$8-b adiabatic pipelined multiplier is designed. Simplified four phase clock generator is also designed to provide supply clocks for adiabatic circuits. All the clock line charge on the capacitive interconnections is recovered to save energy. Adiabatic circuits are designed based on ECRL(efficient charge recovery logic) and are integrated using 0.6${\mu}{\textrm}{m}$ CMOS technology. The efficiency of proposed supply clock generator is better than the previous one by 4~11%. Simulation results show that the power consumption of adiabatic pipelined multiplier is reduced by a factor of 2.6~3.5 compared to a conventional pipelined CMOS multiplier.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.628-636
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• 2010

In this paper, we present a new type high speed parallel multiplier for performing the multiplication of two polynomials using standard basis in the finite fields GF($2^m$). Prior to construct the multiplier circuits, we design the basic cell of vector code generator(VCG) to perform the parallel multiplication of a multiplicand polynomial with a irreducible polynomial and design the partial product result cell(PPC) to generate the result of bit-parallel multiplication with one coefficient of a multiplicative polynomial with VCG circuits. The presented multiplier performs high speed parallel multiplication to connect PPC with VCG. The basic cell of VCG and PPC consists of one AND gate and one XOR gate respectively. Extending this process, we show the design of the generalized circuits for degree m and a simple example of constructing the multiplier circuit over finite fields GF($2^4$). Also, the presented multiplier is simulated by PSpice. The multiplier presented in this paper uses the VCGs and PPCS repeatedly, and is easy to extend the multiplication of two polynomials in the finite fields with very large degree m, and is suitable to VLSL.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.646-649
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• 2002

In this paper, a low-voltage CMOS squarer and a four-quadrant analog multiplier are presented. It is based on a source-coupled pair and a scaled-floating voltage generator which are modified to work as a voltage squaring and a sum/difference circuits. The proposed squarer/multiplier have been simulated with HSPICE, where -3㏈ bandwidth of 10MHz is achieved. The power consumption is about 0.6㎽, from a ${\pm}$1.5V supply, and the total harmonic distortion is less than 0.7%, with a 1.2V peak-to-peak 1MHz input signal.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.267-270
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• 2003

This paper proposes high performance $8{\times}8$ multiplier using current-mode quaternary logic technique. The multiplier is functionally partitioned into the following major sections: partial product generator block(binary-quaternary logic conversion), current-mode quaternary logic full-adder block, quaternary-binary logic conversion block. The proposed multiplier has 4.5ns of propagation delay and 6.1mW of power consumption. Also, this multiplier can easily adapted to binary system by the encoder, the decoder. This circuit is simulated under 0.35um standard CMOS technology, 5uA unit current, and 3.3V supply voltage using Hspice.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.63-70
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• 2014

A low-N phase-locked loop clock generator with frequency multiplier is proposed to improve phase noise characteristic. Delay-variance voltage converter (DVVC) generates output voltages according to the delay variance of delay stages in voltage controlled oscillator. The output voltages of average circuit with the output voltages of DVVC are applied to the delay stages in VCO to reduce jitter. The HSPICE simulation of the proposed phase-locked loop clock generator with a $0.18{\mu}m$ CMOS process shows an 11.3 ps of peak-to-peak jitter.

• Journal of Advanced Navigation Technology
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• v.14 no.1
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• pp.66-73
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• 2010

This paper proposes the frequency multiplier using diplexer based on CRLH transmission line with dualband characteristic. The diplexer is separated the output signals of harmonic generator, which is generated the harmonic signals using nonlinear device. The diplexer consists of the inphase power divider, 0o/90o phase controller and dual-band quadrature hybrid coupler. This send out the selecting output signals of the harmonic signals and suppresses out of signals. To validate a function of multiplier, the harmonic generator and diplexer with 2 GHz and 3 GHz operating frequency range is implemented. As a result, the proposed frequency multiplier is operated normally.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.35-38
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• 2018

This paper describes a low-power MPPT interface for DC-type energy harvesting sources. The proposed circuit consists of an MPPT controller, a bias generator, and a voltage detector. The MPPT controller consists of an MPG (MPPT Pulse Generator) with a schmitt trigger, a logic gate operating according to energy type (light, heat), and a sample/hold circuit. The bias generator is designed by employing a beta multiplier structure, and the voltage detector is implemented using a bulk-driven comparator and a two-stage buffer. The proposed circuit is designed with $0.35{\mu}m$ CMOS process. The simulation results show that the designed circuit consumes less than 100nA of current at an input voltage of less than 3V and the maximum power efficiency is 99.7%. The chip area of the designed circuit is $1151{\mu}m{\times}940{\mu}m$.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.14 no.2
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• pp.46-51
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• 2000

The generation of the intensive ultrasonic waves depend mainly on the energy conversion efficiency depending on high frequency oscillation of the generator and the control performance of stable output depending on load variation, respectively. In this dissertation, a new configuration of ultrasonic generator is specially proposed and designed for improving both efficiency and stability. The generating frequency is turned by a PLL. which is controlled through the detection on phase difference between outputs and currents of the loads and the output amplitude of MOSFET, Q1 are controlled by their products through the multiplier, which results in the control of the amplitude of voltage controlled oscillation. And finally, the proposed and designed ultrasonic generator is composed by the combination of the function in mentioned above. the analysis results of the proposed circuit shows a good agreement between simulations and experiments.