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http://dx.doi.org/10.6109/jkiice.2010.14.3.628

A Study on Design of High-Speed Parallel Multiplier over GF(2m) using VCG  

Seong, Hyeon-Kyeong (상지대학교 컴퓨터정보공학부)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.14, no.3, 2010 , pp. 628-636 More about this Journal
Abstract
In this paper, we present a new type high speed parallel multiplier for performing the multiplication of two polynomials using standard basis in the finite fields GF($2^m$). Prior to construct the multiplier circuits, we design the basic cell of vector code generator(VCG) to perform the parallel multiplication of a multiplicand polynomial with a irreducible polynomial and design the partial product result cell(PPC) to generate the result of bit-parallel multiplication with one coefficient of a multiplicative polynomial with VCG circuits. The presented multiplier performs high speed parallel multiplication to connect PPC with VCG. The basic cell of VCG and PPC consists of one AND gate and one XOR gate respectively. Extending this process, we show the design of the generalized circuits for degree m and a simple example of constructing the multiplier circuit over finite fields GF($2^4$). Also, the presented multiplier is simulated by PSpice. The multiplier presented in this paper uses the VCGs and PPCS repeatedly, and is easy to extend the multiplication of two polynomials in the finite fields with very large degree m, and is suitable to VLSL.
Keywords
Finite fields; GF($2^m$); Parallel multiplier; Standard basis; Vector code generator;
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